vsra

Vector Shift Right and Accumulate

VSRA<c>.<dt> <Qd>, <Qm>, #<imm>

Shifts elements right and adds to the destination accumulator.

Details

Shifts each element in the source register right by the immediate shift amount and accumulates (adds) the shifted result into the corresponding element of the destination register. The shift amount is treated as unsigned. No condition flags are modified. This is a NEON instruction available in both A32 and T32 instruction sets.

Pseudocode Operation

for i = 0 to elements_in_Qd - 1
  shift_amount ← imm6
  shifted ← Qm[i] >> shift_amount
  Qd[i] ← Qd[i] + shifted
endfor

Example

VSRA.dt q0, q2, #16

Encoding

Binary Layout
1111001
U
1
D
imm6
Vd
0001
L
0
M
1
Vm
 
Format NEON Shift
Opcode 0xF2800110
Extension NEON (SIMD)

Operands

  • Qd
    Dest/Acc
  • Qm
    Second source 128-bit SIMD register
  • imm
    Signed immediate value

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2800110 VSRA{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm> A32 1111001 | U | 1 | D | imm6 | Vd | 0001 | L | 0 | M | 1 | Vm
0xF2800150 VSRA{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm> A32 1111001 | U | 1 | D | imm6 | Vd | 0001 | L | 1 | M | 1 | Vm
0xEF800110 VSRA{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm> T32 111 | U | 11111 | D | imm6 | Vd | 0001 | L | 0 | M | 1 | Vm
0xEF800150 VSRA{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm> T32 111 | U | 11111 | D | imm6 | Vd | 0001 | L | 1 | M | 1 | Vm

Description

Vector Shift Right and Accumulate takes each element in a vector, right shifts them by an immediate value, and accumulates the truncated results into the destination vector. For rounded results, see VRSRA. The operand and result elements must all be the same type, and can be any one of: Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            result = Int(Elem[D[m+r],e,esize], unsigned) >> shift_amount;
            Elem[D[d+r],e,esize] = Elem[D[d+r],e,esize] + result;