vsra

Vector Shift Right and Accumulate

VSRA<c>.<dt> <Qd>, <Qm>, #<imm>

Shifts elements right and adds to the destination accumulator.

Pseudocode Operation

for i = 0 to elements_in_Qd - 1
  shift_amount ← imm6
  shifted ← Qm[i] >> shift_amount
  Qd[i] ← Qd[i] + shifted
endfor

Example

VSRA.dt q0, q2, #16

Encoding

Binary Layout

1111001

31:25

U

24

1

23

D

22

imm6

21:16

Vd

15:12

0001

11:8

L

7

0

6

M

5

1

4

Vm

3:0

 

Format NEON Shift

Opcode 0xF2800110

Extension NEON (SIMD)

Operands

• Qd
  Dest/Acc
• Qm
  Second source 128-bit SIMD register
• imm
  Signed immediate value

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xF2800110	VSRA{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm>		A32		1111001 | U | 1 | D | imm6 | Vd | 0001 | L | 0 | M | 1 | Vm
0xF2800150	VSRA{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm>		A32		1111001 | U | 1 | D | imm6 | Vd | 0001 | L | 1 | M | 1 | Vm
0xEF800110	VSRA{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm>		T32		111 | U | 11111 | D | imm6 | Vd | 0001 | L | 0 | M | 1 | Vm
0xEF800150	VSRA{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm>		T32		111 | U | 11111 | D | imm6 | Vd | 0001 | L | 1 | M | 1 | Vm

Description

Vector Shift Right and Accumulate takes each element in a vector, right shifts them by an immediate value, and accumulates the truncated results into the destination vector. For rounded results, see VRSRA. The operand and result elements must all be the same type, and can be any one of: Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            result = Int(Elem[D[m+r],e,esize], unsigned) >> shift_amount;
            Elem[D[d+r],e,esize] = Elem[D[d+r],e,esize] + result;