sunpklo

SVE Signed Unpack Low

SUNPKLO <Zd>.<T>, <Zn>.<Tb>

Unpacks and sign-extends lower half of vector elements.

Pseudocode Operation

for i = 0 to VL/esize_dst-1
  Zd[i+1:i] ← sign_extend(Zn[i+esize_src/2-1:i], esize_dst)

Example

SUNPKLO z0.s.T, z1.s.Tb

Encoding

Binary Layout

00000101

31:24

size

23:22

1100

21:18

001110

15:10

9:5

4:0

Format SVE Permute

Opcode 0x05303800

Extension SVE

Operands

Zd
Destination scalable vector register (SVE)
Zn
First source scalable vector register (SVE)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x05303800	SUNPKLO <Zd>.<T>, <Zn>.<Tb>		A64		00000101 \| size \| 1100 \| 0 \| 0 \| 001110 \| Zn \| Zd

Description

Unpack elements from the lowest or highest half of the source vector and then sign-extend them to place in elements of twice their size within the destination vector. This instruction is unpredicated.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
constant integer hsize = esize DIV 2;
bits(VL) operand = Z[n, VL];
bits(VL) result;

for e = 0 to elements-1
    bits(hsize) element = if hi then Elem[operand, e + elements, hsize] else Elem[operand, e, hsize];
    Elem[result, e, esize] = Extend(element, esize, unsigned);

Z[d, VL] = result;