fadd

Floating-Point Add (Scalar)

FADD <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>

Adds two floating-point values.

Pseudocode Operation

Rd ← FP_Add(Rn, Rm)
if (type == 00) then operands are H-registers (16-bit)
else if (type == 01) then operands are S-registers (32-bit)
else if (type == 10) then operands are D-registers (64-bit)

Example

FADD Dd, Dn, Dm

Encoding

Binary Layout
0
31
0
30
0
29
11110
28:24
00
23:22
1
21
Rm
20:16
001
15:13
0
12
10
11:10
Rn
9:5
Rd
4:0
 
Format FP Data Processing
Opcode 0x1E202800
Extension Floating Point

Operands

  • Hd|Sd|Dd
    Destination SIMD&FP register (half, single or double-precision)
  • Hn|Sn|Dn
    First source SIMD&FP register (half, single or double-precision)
  • Hm|Sm|Dm
    Second source SIMD&FP register (half, single or double-precision)

Related

Other forms of fadd

  • fadd Vector Floating-Point Add
  • fadd SVE Floating-Point Add
  • fadd Floating-Point Add (Half-Precision)
  • fadd Floating-point Add (Single)
  • fadd Floating-point Add (Double)

More in Floating Point

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0E401400 FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 01110 | 0 | 10 | Rm | 00 | 010 | 1 | Rn | Rd
0x0E20D400 FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 011100 | sz | 1 | Rm | 11010 | 1 | Rn | Rd
0x1EE02800 FADD <Hd>, <Hn>, <Hm> A64 0 | 0 | 0 | 11110 | 11 | 1 | Rm | 001 | 0 | 10 | Rn | Rd
0x1E202800 FADD <Sd>, <Sn>, <Sm> A64 0 | 0 | 0 | 11110 | 00 | 1 | Rm | 001 | 0 | 10 | Rn | Rd
0x1E602800 FADD <Dd>, <Dn>, <Dm> A64 0 | 0 | 0 | 11110 | 01 | 1 | Rm | 001 | 0 | 10 | Rn | Rd
0x65188000 FADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const> A64 01100101 | size | 011 | 00 | 0 | 100 | Pg | 0000 | i1 | Zdn
0x65008000 FADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 01100101 | size | 00 | 000 | 0 | 100 | Pg | Zm | Zdn
0x65000000 FADD <Zd>.<T>, <Zn>.<T>, <Zm>.<T> A64 01100101 | size | 0 | Zm | 000 | 00 | 0 | Zn | Zd
0xC1A01C00 FADD ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zm1>.<T>-<Zm2>.<T> } A64 110000011 | sz | 1000000 | Rv | 111 | Zm | 00 | 0 | off3
0xC1A41C00 FADD ZA.H[<Wv>, <offs>{, VGx2}], { <Zm1>.H-<Zm2>.H } A64 110000011 | 0 | 1001000 | Rv | 111 | Zm | 00 | 0 | off3
0xC1A11C00 FADD ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zm1>.<T>-<Zm4>.<T> } A64 110000011 | sz | 1000010 | Rv | 111 | Zm | 000 | 0 | off3
0xC1A51C00 FADD ZA.H[<Wv>, <offs>{, VGx4}], { <Zm1>.H-<Zm4>.H } A64 110000011 | 0 | 1001010 | Rv | 111 | Zm | 000 | 0 | off3

Description

Floating-point Add (scalar). This instruction adds the floating-point values of the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();
bits(esize) operand1 = V[n, esize];
bits(esize) operand2 = V[m, esize];

boolean merge = IsMerging(FPCR);
bits(128) result = if merge then V[n, 128] else Zeros(128);

Elem[result, 0, esize] = FPAdd(operand1, operand2, FPCR);

V[d, 128] = result;