fmsub

Floating-Point Fused Multiply-Subtract (Scalar)

FMSUB <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <Ha|Sa|Da>

Calculates (Vn * Vm) - Va.

Pseudocode Operation

if HaveFPExt() then
  Vd ← FPMulSub(Vn, Vm, Va)
else
  UNDEFINED

Example

FMSUB Dd, Dn, Dm, Da

Encoding

Binary Layout
0
31
0
30
0
29
11111
28:24
00
23:22
0
21
Rm
20:16
1
15
Ra
14:10
Rn
9:5
Rd
4:0
 
Format FP Data Processing
Opcode 0x1F008000
Extension Floating Point

Operands

  • Hd|Sd|Dd
    Destination SIMD&FP register (half, single or double-precision)
  • Hn|Sn|Dn
    First source SIMD&FP register (half, single or double-precision)
  • Hm|Sm|Dm
    Second source SIMD&FP register (half, single or double-precision)
  • Ha|Sa|Da
    Third source (accumulator) SIMD&FP register (half, single or double-precision)

Related

More in Floating Point

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x1FC08000 FMSUB <Hd>, <Hn>, <Hm>, <Ha> A64 0 | 0 | 0 | 11111 | 11 | 0 | Rm | 1 | Ra | Rn | Rd
0x1F008000 FMSUB <Sd>, <Sn>, <Sm>, <Sa> A64 0 | 0 | 0 | 11111 | 00 | 0 | Rm | 1 | Ra | Rn | Rd
0x1F408000 FMSUB <Dd>, <Dn>, <Dm>, <Da> A64 0 | 0 | 0 | 11111 | 01 | 0 | Rm | 1 | Ra | Rn | Rd

Description

Floating-point Fused Multiply-Subtract (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, negates the product, adds that to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();

bits(esize) operanda = V[a, esize];
bits(esize) operand1 = V[n, esize];
bits(esize) operand2 = V[m, esize];

boolean merge = IsMerging(FPCR);
bits(128) result = if merge then V[a, 128] else Zeros(128);

operand1 = FPNeg(operand1, FPCR);
Elem[result, 0, esize] = FPMulAdd(operanda, operand1, operand2, FPCR);

V[d, 128] = result;