vzip
Vector Zip
VZIP<c>.<dt> <Qd>, <Qm>
Interleaves vectors.
Pseudocode Operation
temp_d ← Qd
temp_m ← Qm
for i ← 0 to (128 / (2 * element_width)) - 1:
Qd[2 * i * element_width +: element_width] ← temp_d[i * element_width +: element_width]
Qd[(2 * i + 1) * element_width +: element_width] ← temp_m[i * element_width +: element_width]
Qm[2 * i * element_width +: element_width] ← temp_d[(64 + i) * element_width +: element_width]
Qm[(2 * i + 1) * element_width +: element_width] ← temp_m[(64 + i) * element_width +: element_width]Example
VZIP.dt q0, q2
Encoding
Binary Layout
111100111
31:23
D
22
11
21:20
size
19:18
10
17:16
Vd
15:12
0
11
0011
10:7
1
6
M
5
0
4
Vm
3:0
Operands
-
Qd
Dest/Src1 -
Qm
Second source 128-bit SIMD register
Related
More in NEON (SIMD)
Reference
View in Arm A64 ISA Reference ↗
Arm AArch32 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0xF3B20180 | VZIP{<c>}{<q>}.<dt> <Dd>, <Dm> | A32 | 111100111 | D | 11 | size | 10 | Vd | 0 | 0011 | 0 | M | 0 | Vm | ||
| 0xF3B201C0 | VZIP{<c>}{<q>}.<dt> <Qd>, <Qm> | A32 | 111100111 | D | 11 | size | 10 | Vd | 0 | 0011 | 1 | M | 0 | Vm | ||
| 0xFFB20180 | VZIP{<c>}{<q>}.<dt> <Dd>, <Dm> | T32 | 111111111 | D | 11 | size | 10 | Vd | 0 | 0011 | 0 | M | 0 | Vm | ||
| 0xFFB201C0 | VZIP{<c>}{<q>}.<dt> <Qd>, <Qm> | T32 | 111111111 | D | 11 | size | 10 | Vd | 0 | 0011 | 1 | M | 0 | Vm | ||
| 0xF3B20080 | VZIP{<c>}{<q>}.32 <Dd>, <Dm> | A32 | 111100111 | D | 11 | size | 10 | Vd | 0 | 0001 | 0 | M | 0 | Vm | ||
| 0xFFB20080 | VZIP{<c>}{<q>}.32 <Dd>, <Dm> | T32 | 111111111 | D | 11 | size | 10 | Vd | 0 | 0001 | 0 | M | 0 | Vm |
Description
Vector Zip interleaves the elements of two vectors. The elements of the vectors can be 8-bit, 16-bit, or 32-bit. There is no distinction between data types. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
if quadword_operation then
if d == m then
Q[d>>1] = bits(128) UNKNOWN;
else
bits(256) zipped_q;
for e = 0 to (128 DIV esize) - 1
Elem[zipped_q,2*e,esize] = Elem[Q[d>>1],e,esize];
Elem[zipped_q,2*e+1,esize] = Elem[Q[m>>1],e,esize];
Q[d>>1] = zipped_q<127:0>; Q[m>>1] = zipped_q<255:128>;
else
if d == m then
D[d] = bits(64) UNKNOWN;
else
bits(128) zipped_d;
for e = 0 to (64 DIV esize) - 1
Elem[zipped_d,2*e,esize] = Elem[D[d],e,esize];
Elem[zipped_d,2*e+1,esize] = Elem[D[m],e,esize];
D[d] = zipped_d<63:0>; D[m] = zipped_d<127:64>;