ldaprb

Load-Acquire RCpc Register Byte

LDAPRB <Wt>, [<Xn|SP>]

Loads a byte with Release Consistency (process consistent) Acquire semantics.

Pseudocode Operation

address ← Xn
data ← ZeroExtend([address], 8)
Wt ← data
AcquireBarrier(RCpc)

Example

LDAPRB w3, [x1]

Encoding

Binary Layout
00
31:30
111
29:27
0
26
00
25:24
1
23
0
22
1
21
11111
20:16
1
15
100
14:12
00
11:10
Rn
9:5
Rt
4:0
 
Format Load/Store
Opcode 0x38BFC000
Extension Base (RCpc)

Operands

  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register

Related

More in Base (RCpc)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x38BFC000 LDAPRB <Wt>, [<Xn|SP> {, #0}] A64 00 | 111 | 0 | 00 | 1 | 0 | 1 | 11111 | 1 | 100 | 00 | Rn | Rt

Description

Load-Acquire RCpc Register Byte derives an address from a base register value, loads a byte from the derived address in memory, zero-extends it and writes it to a register. The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that: This difference in memory ordering is not described in the pseudocode. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(8) data;

AccessDescriptor accdesc = CreateAccDescLDAcqPC(tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

data = Mem[address, 1, accdesc];
X[t, 32] = ZeroExtend(data, 32);