ldr

Load Register PC-Relative (A32)

LDR<c> <Rt>, <label>

Loads a word from a label.

Details

Loads a 32-bit word from a memory address computed as the sum of the current PC and a label offset. The offset is encoded as a 12-bit immediate, with the direction (add/subtract) controlled by the U bit. No condition flags are affected. Execution state: A32 only; label must be within ±4KB of the current instruction.

Pseudocode Operation

if U == 1 then
  address ← Align(PC, 4) + imm12
else
  address ← Align(PC, 4) - imm12
Rt ← [address]

Example

LDR r3, label

Encoding

Binary Layout
cond
010
P
U
0
W
1
1111
Rt
imm12
 
Format Load Literal
Opcode 0x041F0000
Extension A32 (Base)

Operands

  • Rt
    Transfer general-purpose register (load/store)
  • label
    Label

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x05100000 LDR{<c>}{<q>} <Rt>, [<Rn> {, #{+/-}<imm>}] A32 cond | 010 | 1 | U | 0 | 0 | 1 | Rn | Rt | imm12
0x04100000 LDR{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm> A32 cond | 010 | 0 | U | 0 | 0 | 1 | Rn | Rt | imm12
0x05300000 LDR{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]! A32 cond | 010 | 1 | U | 0 | 1 | 1 | Rn | Rt | imm12
0x6800 LDR{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] T32 011 | 0 | 1 | imm5 | Rn | Rt
0x9800 LDR{<c>}{<q>} <Rt>, [SP{, #{+}<imm>}] T32 1001 | 1 | Rt | imm8
0xF8D00000 LDR{<c>}.W <Rt>, [<Rn> {, #{+}<imm>}] T32 111110001 | 10 | 1 | Rn | Rt | imm12
0xF8500C00 LDR{<c>}{<q>} <Rt>, [<Rn> {, #-<imm>}] T32 111110000 | 10 | 1 | Rn | Rt | 1 | 1 | 0 | 0 | imm8
0xF8500900 LDR{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm> T32 111110000 | 10 | 1 | Rn | Rt | 1 | 0 | U | 1 | imm8
0xF8500D00 LDR{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<imm>]! T32 111110000 | 10 | 1 | Rn | Rt | 1 | 1 | U | 1 | imm8
0x041F0000 LDR{<c>}{<q>} <Rt>, <label> A32 cond | 010 | P | U | 0 | W | 1 | 1111 | Rt | imm12
0x4800 LDR{<c>}{<q>} <Rt>, <label> T32 01001 | Rt | imm8
0xF85F0000 LDR{<c>}.W <Rt>, <label> T32 11111000 | U | 10 | 1 | 1111 | Rt | imm12
0x07100000 LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] A32 cond | 011 | 1 | U | 0 | 0 | 1 | Rn | Rt | imm5 | stype | 0 | Rm
0x06100000 LDR{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} A32 cond | 011 | 0 | U | 0 | 0 | 1 | Rn | Rt | imm5 | stype | 0 | Rm

Description

Load Register (literal) calculates an address from the PC value and an immediate offset, loads a word from memory, and writes it to a register. For information about memory accesses see Memory accesses.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    base = Align(PC,4);
    address = if add then (base + imm32) else (base - imm32);
    data = MemU[address,4];
    if t == 15 then
        if address<1:0> == '00' then
            LoadWritePC(data);
        else
            UNPREDICTABLE;
    else
        R[t] = data;