vuzp

Vector Unzip

VUZP<c>.<dt> <Qd>, <Qm>

De-interleaves vectors.

Details

De-interleaves elements from two 128-bit NEON vectors by extracting all even-indexed or all odd-indexed elements and placing them into Qd and Qm respectively. Element size is determined by <dt>. No flags are affected. Execution is restricted to A32/T32 with NEON support.

Pseudocode Operation

temp_d ← Qd
temp_m ← Qm
for i ← 0 to (128 / (2 * element_width)) - 1:
  Qd[i * element_width +: element_width] ← temp_d[(2 * i) * element_width +: element_width]
  Qd[(64 + i) * element_width +: element_width] ← temp_m[(2 * i) * element_width +: element_width]
  Qm[i * element_width +: element_width] ← temp_d[(2 * i + 1) * element_width +: element_width]
  Qm[(64 + i) * element_width +: element_width] ← temp_m[(2 * i + 1) * element_width +: element_width]

Example

VUZP.dt q0, q2

Encoding

Binary Layout
111100111
D
11
size
10
Vd
0
0010
1
M
0
Vm
 
Format NEON 2-Reg
Opcode 0xF3B20140
Extension NEON (SIMD)

Operands

  • Qd
    Dest/Src1
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3B20100 VUZP{<c>}{<q>}.<dt> <Dd>, <Dm> A32 111100111 | D | 11 | size | 10 | Vd | 0 | 0010 | 0 | M | 0 | Vm
0xF3B20140 VUZP{<c>}{<q>}.<dt> <Qd>, <Qm> A32 111100111 | D | 11 | size | 10 | Vd | 0 | 0010 | 1 | M | 0 | Vm
0xFFB20100 VUZP{<c>}{<q>}.<dt> <Dd>, <Dm> T32 111111111 | D | 11 | size | 10 | Vd | 0 | 0010 | 0 | M | 0 | Vm
0xFFB20140 VUZP{<c>}{<q>}.<dt> <Qd>, <Qm> T32 111111111 | D | 11 | size | 10 | Vd | 0 | 0010 | 1 | M | 0 | Vm
0xF3B20080 VUZP{<c>}{<q>}.32 <Dd>, <Dm> A32 111100111 | D | 11 | size | 10 | Vd | 0 | 0001 | 0 | M | 0 | Vm
0xFFB20080 VUZP{<c>}{<q>}.32 <Dd>, <Dm> T32 111111111 | D | 11 | size | 10 | Vd | 0 | 0001 | 0 | M | 0 | Vm

Description

Vector Unzip de-interleaves the elements of two vectors. The elements of the vectors can be 8-bit, 16-bit, or 32-bit. There is no distinction between data types. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    if quadword_operation then
        if d == m then
            Q[d>>1] = bits(128) UNKNOWN;
        else
            zipped_q = Q[m>>1]:Q[d>>1];
            for e = 0 to (128 DIV esize) - 1
                Elem[Q[d>>1],e,esize] = Elem[zipped_q,2*e,esize];
                Elem[Q[m>>1],e,esize] = Elem[zipped_q,2*e+1,esize];
    else
        if d == m then
            D[d] = bits(64) UNKNOWN;
        else
            zipped_d = D[m]:D[d];
            for e = 0 to (64 DIV esize) - 1
                Elem[D[d],e,esize] = Elem[zipped_d,2*e,esize];
                Elem[D[m],e,esize] = Elem[zipped_d,2*e+1,esize];