sudot
Signed-Unsigned Dot Product (NEON)
SUDOT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>[<index>]
Dot product of Signed Int8 and Unsigned Int8 (Indexed).
Details
Performs a signed-unsigned 8-bit integer dot product with an indexed operand, multiplying signed Int8 elements from Vn with unsigned Int8 elements from a specific 32-bit lane of Vm and accumulating into 32-bit integer lanes of Vd. This instruction operates on 128-bit NEON vectors and requires the FEAT_I8MM architectural feature. No condition flags are affected; this is an AArch64-only instruction.
Pseudocode Operation
// Vm is indexed; extract the 32-bit lane containing 4 unsigned Int8 values
for e = 0 to (128 / 32) - 1
lane_data ← Vm[32×index + 0 : 32×index + 31]
Vd[e] ← Vd[e] + (sint(Vn[4×e]) × uint(lane_data[7:0]) +
sint(Vn[4×e+1]) × uint(lane_data[15:8]) +
sint(Vn[4×e+2]) × uint(lane_data[23:16]) +
sint(Vn[4×e+3]) × uint(lane_data[31:24]))
// Each Vd[e] is a 32-bit signed resultExample
SUDOT v0.4s.T, v1.4s.T, v2.4s.T[index]
Encoding
Binary Layout
0
Q
0
01111
0
0
L
M
Rm
1111
H
0
Rn
Rd
Operands
-
Vd
Destination SIMD/FP vector register -
Vn
Signed -
Vm
Unsigned
Reference (Arm A64 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x0F00F000 | SUDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.4B[<index>] | A64 | 0 | Q | 0 | 01111 | 0 | 0 | L | M | Rm | 1111 | H | 0 | Rn | Rd | ||
| 0x44A01C00 | SUDOT <Zda>.S, <Zn>.B, <Zm>.B[<imm>] | A64 | 01000100 | 1 | 0 | 1 | i2 | Zm | 00011 | 1 | Zn | Zda | ||
| 0xC1501038 | SUDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] | A64 | 110000010101 | Zm | 0 | Rv | 1 | i2 | Zn | 1 | 1 | 1 | off3 | ||
| 0xC1509038 | SUDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>] | A64 | 110000010101 | Zm | 1 | Rv | 1 | i2 | Zn | 0 | 1 | 1 | 1 | off3 | ||
| 0xC1201418 | SUDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B | A64 | 11 | 0000010010 | Zm | 0 | Rv | 101 | Zn | 1 | 1 | off3 | ||
| 0xC1301418 | SUDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B | A64 | 11 | 0000010011 | Zm | 0 | Rv | 101 | Zn | 1 | 1 | off3 |
Description
Dot product index form with signed and unsigned integers. This instruction performs the dot product of the four signed 8-bit integer values in each 32-bit element of the first source register with the four unsigned 8-bit integer values in an indexed 32-bit element of the second source register, accumulating the result into the corresponding 32-bit element of the destination vector.
From Armv8.2 to Armv8.5, this is an OPTIONAL instruction. From Armv8.6 it is mandatory for implementations that include Advanced SIMD to support it. ID_AA64ISAR1_EL1.I8MM indicates whether this instruction is supported.
Operation
CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(128) operand2 = V[m, 128];
bits(datasize) operand3 = V[d, datasize];
bits(datasize) result;
for e = 0 to elements-1
bits(32) res = Elem[operand3, e, 32];
for b = 0 to 3
integer element1 = Int(Elem[operand1, 4*e+b, 8], op1_unsigned);
integer element2 = Int(Elem[operand2, 4*i+b, 8], op2_unsigned);
res = res + element1 * element2;
Elem[result, e, 32] = res;
V[d, datasize] = result;