vaddw

Vector Add Wide

VADDW<c>.<dt> <Qd>, <Qn>, <Dm>

Adds N-bit vector to 2N-bit vector.

Details

Adds a 64-bit vector of N-bit elements to a 128-bit vector of 2N-bit elements, with the narrow operand implicitly widened before addition. The result is stored in the 128-bit destination. This instruction combines widening and addition in a single operation. No flags are affected.

Pseudocode Operation

for i = 0 to pairs-1
  Qd[i] ← Qn[i] + widen(Dm[i])

Example

VADDW.dt q0, q1, d2

Encoding

Binary Layout
1111001
U
1
D
size
Vn
Vd
000
1
N
0
M
0
Vm
 
Format NEON 3-Reg
Opcode 0xF2800100
Extension NEON (SIMD)

Operands

  • Qd
    Dest Wide
  • Qn
    Src Wide
  • Dm
    Src Narrow

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2800100 VADDW{<c>}{<q>}.<dt> {<Qd>,} <Qn>, <Dm> A32 1111001 | U | 1 | D | size | Vn | Vd | 000 | 1 | N | 0 | M | 0 | Vm
0xEF800100 VADDW{<c>}{<q>}.<dt> {<Qd>,} <Qn>, <Dm> T32 111 | U | 11111 | D | size | Vn | Vd | 000 | 1 | N | 0 | M | 0 | Vm

Description

Vector Add Wide adds corresponding elements in one quadword and one doubleword vector, and places the results in a quadword vector. Before adding, it sign-extends or zero-extends the elements of the doubleword operand. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for e = 0 to elements-1
        integer op1;
        if is_vaddw then
            op1 = Int(Elem[Qin[n>>1],e,2*esize], unsigned);
        else
            op1 = Int(Elem[Din[n],e,esize], unsigned);
        result = op1 + Int(Elem[Din[m],e,esize],unsigned);
        Elem[Q[d>>1],e,2*esize] = result<2*esize-1:0>;