addv

Vector Add Across

ADDV <V><d>, <Vn>.<T>

Adds all elements of the vector into a scalar result.

Pseudocode Operation

result ← 0
for i = 0 to elements_in_vector - 1
  result ← result + Vn[i]
Vd[result_element_index] ← result
Vd[upper_bits] ← 0

Example

ADDV Vd, v1.4s.T

Encoding

Binary Layout

0

31

Q

30

0

29

01110

28:24

size

23:22

11000

21:17

11011

16:12

10

11:10

Rn

9:5

Rd

4:0

 

Format SIMD Across Lane

Opcode 0x0E31B800

Extension NEON (SIMD)

Operands

• Vd
  Dest Scalar
• Vn
  Src Vector

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x0E31B800	ADDV <V><d>, <Vn>.<T>		A64		0 | Q | 0 | 01110 | size | 11000 | 11011 | 10 | Rn | Rd

Description

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n, datasize];
V[d, esize] = IntReduce(ReduceOp_ADD, operand, esize);