orv

SVE Bitwise OR Reduction

ORV <Vd>, <Pg>, <Zn>.<T>

ORs all active elements into a scalar.

Pseudocode Operation

bits(esize) result = 0;
for i = 0 to VL/esize - 1
  if Pg[i] == '1' then
    element = Zn[i*esize +: esize];
    result = result OR element;
Vd[0 +: esize] ← result;

Example

ORV v0.4s, p0/m, z1.s.T

Encoding

Binary Layout

00000100

31:24

size

23:22

0110

21:18

001

15:13

12:10

9:5

4:0

Format SVE Reduction

Opcode 0x04182000

Extension SVE

Operands

Vd
Dest Scalar
Pg
Mask
Zn
Vector

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x04182000	ORV <V><d>, <Pg>, <Zn>.<T>		A64		00000100 \| size \| 0110 \| 0 \| 0 \| 001 \| Pg \| Zn \| Vd

Description

Bitwise inclusive OR horizontally across all lanes of a vector, and place the result in the SIMD&FP scalar destination register. Inactive elements in the source vector are treated as zero.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(esize) result = Zeros(esize);

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        result = result OR Elem[operand, e, esize];

V[d, esize] = result;

orv