neg

SVE Negate

NEG <Zdn>.<T>, <Pg>/M, <Zdn>.<T>

Negates integers.

Pseudocode Operation

for e = 0 to VL/getElementSize(T)-1
  if Pg[e] == 1 then
    Zdn[e] ← -Zdn[e]
  end if
end for

Example

NEG z0.s.T, p0/m/M, z0.s.T

Encoding

Binary Layout

00000100

31:24

size

23:22

010

21:19

18:17

101

15:13

12:10

9:5

4:0

Format SVE Integer Unary

Opcode 0x0417A000

Extension SVE

Operands

Zdn
Dest/Src
Pg
Mask

Other forms of neg

neg Vector Negate

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x7EE0B800	NEG D<d>, D<n>	A64	01 \| 1 \| 11110 \| 11 \| 10000 \| 01011 \| 10 \| Rn \| Rd
0x2E20B800	NEG <Vd>.<T>, <Vn>.<T>	A64	0 \| Q \| 1 \| 01110 \| size \| 10000 \| 01011 \| 10 \| Rn \| Rd
0x4B0003E0	NEG <Wd>, <Wm>{, <shift> #<amount>}	A64	0 \| 1 \| 0 \| 01011 \| shift \| 0 \| Rm \| imm6 \| 11111 \| Rd
0xCB0003E0	NEG <Xd>, <Xm>{, <shift> #<amount>}	A64	1 \| 1 \| 0 \| 01011 \| shift \| 0 \| Rm \| imm6 \| 11111 \| Rd
0x0417A000	NEG <Zd>.<T>, <Pg>/M, <Zn>.<T>	A64	00000100 \| size \| 010 \| 11 \| 1 \| 101 \| Pg \| Zn \| Zd

Description

Negate the signed integer value in each active element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) result = Z[d, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        integer element = SInt(Elem[operand, e, esize]);
        element = -element;
        Elem[result, e, esize] = element<esize-1:0>;

Z[d, VL] = result;

neg