bic

Vector Bitwise Bit Clear

BIC <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

ANDs Vd with NOT of Vm.

Pseudocode Operation

for i = 0 to (128 >> (if Q then 0 else 1)) - 1:
  Vd[i] ← Vn[i] AND NOT(Vm[i]);

Example

BIC v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
31
Q
30
0
29
01110
28:24
01
23:22
1
21
Rm
20:16
00011
15:11
1
10
Rn
9:5
Rd
4:0
 
Format SIMD Three Register
Opcode 0x0E601C00
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Related

Other forms of bic

  • bic Bitwise Bit Clear (Shifted Register)
  • bic Bitwise Bit Clear (Shifted Register 64-bit)
  • bic SVE Bitwise Bit Clear (Predicated)
  • bic Bit Clear (A32)

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2F009400 BIC <Vd>.<T>, #<imm8>{, LSL #<amount>} A64 0 | Q | 1 | 0111100000 | a | b | c | cmode | 0 | 1 | d | e | f | g | h | Rd
0x2F001400 BIC <Vd>.<T>, #<imm8>{, LSL #<amount>} A64 0 | Q | 1 | 0111100000 | a | b | c | cmode | 0 | 1 | d | e | f | g | h | Rd
0x0E601C00 BIC <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 01110 | 01 | 1 | Rm | 00011 | 1 | Rn | Rd
0x05800000 BIC <Zdn>.<T>, <Zdn>.<T>, #<const> A64 00000101 | 1 | 0 | 0000 | imm13 | Zdn
0x0A200000 BIC <Wd>, <Wn>, <Wm>{, <shift> #<amount>} A64 0 | 00 | 01010 | shift | 1 | Rm | imm6 | Rn | Rd
0x8A200000 BIC <Xd>, <Xn>, <Xm>{, <shift> #<amount>} A64 1 | 00 | 01010 | shift | 1 | Rm | imm6 | Rn | Rd
0x25004010 BIC <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B A64 00100101 | 0 | 0 | 00 | Pm | 01 | Pg | 0 | Pn | 1 | Pd
0x041B0000 BIC <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 00000100 | size | 011 | 01 | 1 | 000 | Pg | Zm | Zdn
0x04E03000 BIC <Zd>.D, <Zn>.D, <Zm>.D A64 00000100 | 1 | 1 | 1 | Zm | 001100 | Zn | Zd

Description

Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&FP register and the complement of the second source SIMD&FP register, and writes the result to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;

operand2 = NOT(operand2);

result = operand1 AND operand2;
V[d, datasize] = result;