ands

Bitwise AND and Set Flags (Shifted Register 64-bit)

ANDS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}

Bitwise AND shifted register, updates flags (64-bit).

Details

The Bitwise AND and Set Flags instruction bitwise AND shifted register, updates flags (64-bit).

Pseudocode Operation

Xd ← Xn AND Xm

Example

ANDS x0, x1, x2

Encoding

Binary Layout
11101010
00
Rm
imm6
Rn
Rd
 
Format Logical (Register)
Opcode 0xEA000000
Extension Base

Operands

  • Xd
    Destination 64-bit integer register
  • Xn
    First source / base 64-bit integer register
  • Xm
    Second source / offset 64-bit integer register