stlexh

Store Release Exclusive Halfword (A32)

STLEXH<c> <Rd>, <Rt>, [<Rn>]

Stores a halfword with Release semantics if exclusive.

Details

Stores a halfword to memory with Release semantics if the exclusive monitor is set for the address. Writes a status value (0=success, 1=failure) to Rd and the value from Rt to the memory location addressed by Rn. This is an exclusive store with memory ordering guarantees. No condition flags are affected. Execution state: A32 only; requires privilege level dependent on the accessed address.

Pseudocode Operation

if ExclusiveMonitorsPass(address=Rn, size=2) then
  [Rn] ← Rt[15:0]
  Rd ← 0
  ClearExclusiveMonitors()
else
  Rd ← 1

Example

STLEXH r0, r3, [r1]

Encoding

Binary Layout
cond
00011
11
0
Rn
Rd
1
1
1
0
1001
Rt
 
Format Store Excl
Opcode 0x01E00E90
Extension A32 (Atomic)

Operands

  • Rd
    Status
  • Rt
    Transfer general-purpose register (load/store)
  • Rn
    First source / base general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x01E00E90 STLEXH{<c>}{<q>} <Rd>, <Rt>, [<Rn>] A32 cond | 00011 | 11 | 0 | Rn | Rd | 1 | 1 | 1 | 0 | 1001 | Rt
0xE8C00FD0 STLEXH{<c>}{<q>} <Rd>, <Rt>, [<Rn>] T32 11101000110 | 0 | Rn | Rt | 1111 | 1 | 1 | 01 | Rd

Description

Store-Release Exclusive Halfword stores a halfword from a register to memory if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[n];
    if AArch32.ExclusiveMonitorsPass(address,2) then
        MemO[address, 2] = R[t]<15:0>;
        R[d] = ZeroExtend('0', 32);
    else
        R[d] = ZeroExtend('1', 32);