sha256h
SHA256 Hash Part 1 (A64)
SHA256H <Qd>, <Qn>, <Vm>.4S
SHA256 hash part 1 (AArch64 NEON).
Pseudocode Operation
hash_state ← SHA256HashPart1(Qn, Vm.4S)
Qd ← hash_state
Example
SHA256H q0, q1, v2.4s.4S
Encoding
Binary Layout
01011110
31:24
00
23:22
0
21
Rm
20:16
010
15:13
0
12
00
11:10
Rn
9:5
Rd
4:0
Operands
-
Qd
Destination 128-bit SIMD register -
Qn
First source 128-bit SIMD register -
Vm
Second source SIMD/FP vector register
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x5E004000 | SHA256H <Qd>, <Qn>, <Vm>.4S | A64 | 01011110 | 00 | 0 | Rm | 010 | 0 | 00 | Rn | Rd |
Description
SHA256 hash update (part 1).
Operation
AArch64.CheckFPAdvSIMDEnabled(); bits(128) result; result = SHA256hash(V[d, 128], V[n, 128], V[m, 128], TRUE); V[d, 128] = result;