sm3partw1

SM3 Part Word 1 (A32)

SM3PARTW1.32 <Qd>, <Qn>, <Qm>

SM3 schedule update part 1.

Details

SM3 Part Word 1 performs the first part of SM3 message schedule update, computing intermediate values from the previous message schedule words. This instruction operates on three 128-bit registers and does not affect condition flags. The instruction is A32-only and requires the Crypto SM3 extension; it generates an Undefined Instruction exception if executed without the extension enabled.

Pseudocode Operation

Qd ← SM3_PARTW1(Qn, Qm)

Example

SM3PARTW1.32 q0, q1, q2

Encoding

Binary Layout
11001110011
Rm
1
1
00
00
Rn
Rd
 
Format Crypto 3-Reg
Opcode 0xCE60C000
Extension Crypto (SM3)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xCE60C000 SM3PARTW1 <Vd>.4S, <Vn>.4S, <Vm>.4S A64 11001110011 | Rm | 1 | 1 | 00 | 00 | Rn | Rd

Description

SM3PARTW1 takes three 128-bit vectors from the three source SIMD&FP registers and returns a 128-bit result in the destination SIMD&FP register. The result is obtained by a three-way exclusive-OR of the elements within the input vectors with some fixed rotations, see the Operation pseudocode for more information. This instruction is implemented only when FEAT_SM3 is implemented.

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(128) Vm = V[m, 128];
bits(128) Vn = V[n, 128];
bits(128) Vd = V[d, 128];
bits(128) result;

result<95:0> = (Vd EOR Vn)<95:0> EOR (ROL(Vm<127:96>, 15):ROL(Vm<95:64>, 15):ROL(Vm<63:32>, 15));

for i = 0 to 3
    if i == 3 then
        result<127:96> = (Vd EOR Vn)<127:96> EOR (ROL(result<31:0>, 15));
    result<(32*i)+31:(32*i)> = (result<(32*i)+31:(32*i)> EOR ROL(result<(32*i)+31:(32*i)>, 15) EOR ROL(result<(32*i)+31:(32*i)>, 23));
V[d, 128] = result;