fcvt

Floating-Point Convert (Scalar)

FCVT <Hd|Sd|Dd>, <Hn|Sn|Dn>

Converts between float precisions (e.g., Half <-> Single <-> Double).

Pseudocode Operation

operand ← Vn
result ← ConvertFP(operand, source_precision, destination_precision, FPCR.RMode)
Vd ← result

Example

FCVT Dd, Dn

Encoding

Binary Layout

11110

28:24

23:22

10001

21:17

16:15

10000

14:10

9:5

4:0

Format FP Conversion

Opcode 0x1EE24000

Extension Floating Point

Operands

Hd|Sd|Dd
Destination SIMD&FP register (half, single or double-precision)
Hn|Sn|Dn
First source SIMD&FP register (half, single or double-precision)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x1EE24000	FCVT <Sd>, <Hn>	A64	0 \| 0 \| 0 \| 11110 \| 11 \| 10001 \| 00 \| 10000 \| Rn \| Rd
0x1EE2C000	FCVT <Dd>, <Hn>	A64	0 \| 0 \| 0 \| 11110 \| 11 \| 10001 \| 01 \| 10000 \| Rn \| Rd
0x1E23C000	FCVT <Hd>, <Sn>	A64	0 \| 0 \| 0 \| 11110 \| 00 \| 10001 \| 11 \| 10000 \| Rn \| Rd
0x1E22C000	FCVT <Dd>, <Sn>	A64	0 \| 0 \| 0 \| 11110 \| 00 \| 10001 \| 01 \| 10000 \| Rn \| Rd
0x1E63C000	FCVT <Hd>, <Dn>	A64	0 \| 0 \| 0 \| 11110 \| 01 \| 10001 \| 11 \| 10000 \| Rn \| Rd
0x1E624000	FCVT <Sd>, <Dn>	A64	0 \| 0 \| 0 \| 11110 \| 01 \| 10001 \| 00 \| 10000 \| Rn \| Rd
0xC1A0E000	FCVT { <Zd1>.S-<Zd2>.S }, <Zn>.H	A64	1100000110100000111000 \| Zn \| Zd \| 0
0xC124E000	FCVT <Zd>.B, { <Zn1>.H-<Zn2>.H }	A64	110000010 \| 0 \| 100100111000 \| Zn \| 0 \| Zd
0xC134E000	FCVT <Zd>.B, { <Zn1>.S-<Zn4>.S }	A64	1100000100110100111000 \| Zn \| 0 \| 0 \| Zd
0xC120E000	FCVT <Zd>.H, { <Zn1>.S-<Zn2>.S }	A64	110000010 \| 0 \| 100000111000 \| Zn \| 0 \| Zd
0x6589A000	FCVT <Zd>.S, <Pg>/M, <Zn>.H	A64	01100101 \| 1 \| 0 \| 0010 \| 0 \| 1 \| 101 \| Pg \| Zn \| Zd
0x65C9A000	FCVT <Zd>.D, <Pg>/M, <Zn>.H	A64	01100101 \| 1 \| 1 \| 0010 \| 0 \| 1 \| 101 \| Pg \| Zn \| Zd
0x6588A000	FCVT <Zd>.H, <Pg>/M, <Zn>.S	A64	01100101 \| 1 \| 0 \| 0010 \| 0 \| 0 \| 101 \| Pg \| Zn \| Zd
0x65CBA000	FCVT <Zd>.D, <Pg>/M, <Zn>.S	A64	01100101 \| 1 \| 1 \| 0010 \| 1 \| 1 \| 101 \| Pg \| Zn \| Zd

Description

Floating-point Convert precision (scalar). This instruction converts the floating-point value in the SIMD&FP source register to the precision for the destination register data type using the rounding mode that is determined by the FPCR and writes the result to the SIMD&FP destination register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();

bits(srcsize) operand = V[n, srcsize];
boolean merge = IsMerging(FPCR);
bits(128) result = if merge then V[d, 128] else Zeros(128);

Elem[result, 0, dstsize] = FPConvert(operand, FPCR, dstsize);

V[d, 128] = result;