fcvtl

Vector Floating-Point Convert Long

FCVTL <Vd>.<Td>, <Vn>.<Ts>

Converts narrow floats to wide floats (e.g., Half -> Single).

Details

Converts floating-point elements from a narrower format to a wider format (e.g., float16 to float32, or float32 to float64). The lower half (or upper half if Q=1) of the source vector is converted and stored in the destination vector. No condition flags are affected. Available in AArch64 NEON.

Pseudocode Operation

if sz == 0 then
  for i = 0 to elements_in_vector - 1:
    Vd[i] ← ConvertFloat16ToFloat32(Vn[i])  // Half to Single
else
  for i = 0 to elements_in_vector - 1:
    Vd[i] ← ConvertFloat32ToFloat64(Vn[i])  // Single to Double

Example

FCVTL v0.4s.Td, v1.4s.Ts

Encoding

Binary Layout
0
Q
0
011100
sz
10000
10111
10
Rn
Rd
 
Format SIMD Two Register
Opcode 0x0E217800
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0E217800 FCVTL{2} <Vd>.<Ta>, <Vn>.<Tb> A64 0 | Q | 0 | 011100 | sz | 10000 | 10111 | 10 | Rn | Rd
0xC1A0E001 FCVTL { <Zd1>.S-<Zd2>.S }, <Zn>.H A64 1100000110100000111000 | Zn | Zd | 1

Description

Floating-point Convert to higher precision Long (vector). This instruction reads each element in a vector in the SIMD&FP source register, converts each value to double the precision of the source element using the rounding mode that is determined by the FPCR, and writes each result to the equivalent element of the vector in the SIMD&FP destination register. Where the operation lengthens a 64-bit vector to a 128-bit vector, the FCVTL2 variant operates on the elements in the top 64 bits of the source register. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = Vpart[n, part, datasize];
bits(2*datasize) result;

for e = 0 to elements-1
    Elem[result, e, 2*esize] = FPConvert(Elem[operand, e, esize], FPCR, 2 * esize);

V[d, 2*datasize] = result;