stlex

Store Release Exclusive (A32)

STLEX<c> <Rd>, <Rt>, [<Rn>]

Stores a word with Release Exclusive semantics.

Details

Atomically stores a 32-bit word to memory with Release semantics and exclusive access, writing status to Rd. This A32 instruction is used for inter-processor synchronization and memory ordering. The status register Rd is written with 0 on success or 1 on failure; no condition flags are affected.

Pseudocode Operation

if ExclusiveAccess[Rn] then
  [Rn] ← Rt
  Rd ← 0
  ClearExclusiveAccess()
else
  Rd ← 1

Example

STLEX r0, r3, [r1]

Encoding

Binary Layout
cond
00011
00
0
Rn
Rd
1
1
1
0
1001
Rt
 
Format Load/Store
Opcode 0x01800E90
Extension A32 (Atomic)

Operands

  • Rd
    Status
  • Rt
    Transfer general-purpose register (load/store)
  • Rn
    First source / base general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x01800E90 STLEX{<c>}{<q>} <Rd>, <Rt>, [<Rn>] A32 cond | 00011 | 00 | 0 | Rn | Rd | 1 | 1 | 1 | 0 | 1001 | Rt
0xE8C00FE0 STLEX{<c>}{<q>} <Rd>, <Rt>, [<Rn>] T32 11101000110 | 0 | Rn | Rt | 1111 | 1 | 1 | 10 | Rd

Description

Store-Release Exclusive Word stores a word from a register to memory if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[n];
    if AArch32.ExclusiveMonitorsPass(address,4) then
        MemO[address, 4] = R[t];
        R[d] = ZeroExtend('0', 32);
    else
        R[d] = ZeroExtend('1', 32);