rbit

SVE Reverse Bits

RBIT <Zd>.<T>, <Pg>/M, <Zn>.<T>

Reverses bits in each element.

Pseudocode Operation

for i = 0 to VL/esize-1
  if Pg[i] then
    Zd[i+1:i] ← reverse_bits(Zn[i+1:i], esize)
  else
    Zd[i+1:i] ← Zd[i+1:i]

Example

RBIT z0.s.T, p0/m/M, z1.s.T

Encoding

Binary Layout

00000101

31:24

size

23:22

1001

21:18

1

17

1

16

100

15:13

Pg

12:10

Zn

9:5

Zd

4:0

 

Format SVE Permute

Opcode 0x05278000

Extension SVE

Operands

• Zd
  Destination scalable vector register (SVE)
• Pg
  Mask
• Zn
  First source scalable vector register (SVE)

Related

Other forms of rbit

• rbit Reverse Bits
• rbit Reverse Bits (Thumb)
• rbit Reverse Bits (64-bit)
• rbit Reverse Bits (A32)

Across architectures

Count Trailing Zeros : how x86, ARM, RISC-V, and PowerISA each do this.

More in SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x2E605800	RBIT <Vd>.<T>, <Vn>.<T>		A64		0 | Q | 1 | 01110 | 01 | 10000 | 00101 | 10 | Rn | Rd
0x5AC00000	RBIT <Wd>, <Wn>		A64		0 | 1 | 0 | 11010110 | 00000 | 000000 | Rn | Rd
0xDAC00000	RBIT <Xd>, <Xn>		A64		1 | 1 | 0 | 11010110 | 00000 | 000000 | Rn | Rd
0x05278000	RBIT <Zd>.<T>, <Pg>/M, <Zn>.<T>		A64		00000101 | size | 1001 | 1 | 1 | 100 | Pg | Zn | Zd

Description

Reverse bits in each active element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) result = Z[d, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        bits(esize) element = Elem[operand, e, esize];
        Elem[result, e, esize] = BitReverse(element);

Z[d, VL] = result;