rbit

SVE Reverse Bits

RBIT <Zd>.<T>, <Pg>/M, <Zn>.<T>

Reverses bits in each element.

Details

Reverses the bit order within each SVE vector element, operating under predicate control. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; each element's bits are reversed such that bit 0 becomes the MSB and the MSB becomes bit 0.

Pseudocode Operation

for i = 0 to VL/esize-1
  if Pg[i] then
    Zd[i+1:i] ← reverse_bits(Zn[i+1:i], esize)
  else
    Zd[i+1:i] ← Zd[i+1:i]

Example

RBIT z0.s.T, p0/m/M, z1.s.T

Encoding

Binary Layout
00000101
size
1001
1
1
100
Pg
Zn
Zd
 
Format SVE Permute
Opcode 0x05278000
Extension SVE

Operands

  • Zd
    Destination scalable vector register (SVE)
  • Pg
    Mask
  • Zn
    First source scalable vector register (SVE)

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2E605800 RBIT <Vd>.<T>, <Vn>.<T> A64 0 | Q | 1 | 01110 | 01 | 10000 | 00101 | 10 | Rn | Rd
0x5AC00000 RBIT <Wd>, <Wn> A64 0 | 1 | 0 | 11010110 | 00000 | 000000 | Rn | Rd
0xDAC00000 RBIT <Xd>, <Xn> A64 1 | 1 | 0 | 11010110 | 00000 | 000000 | Rn | Rd
0x05278000 RBIT <Zd>.<T>, <Pg>/M, <Zn>.<T> A64 00000101 | size | 1001 | 1 | 1 | 100 | Pg | Zn | Zd

Description

Reverse bits in each active element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) result = Z[d, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        bits(esize) element = Elem[operand, e, esize];
        Elem[result, e, esize] = BitReverse(element);

Z[d, VL] = result;