vqrshrn

Vector Saturating Rounding Shift Right Narrow

VQRSHRN<c>.<dt> <Dd>, <Qm>, #<imm>

Shifts right, saturates, rounds, and narrows.

Pseudocode Operation

shift_amount ← imm6
for i = 0 to narrow_elements-1 do
  wide_value ← Qm[i]
  rounding_bit ← wide_value[shift_amount-1]
  shifted ← wide_value >> shift_amount
  rounded ← shifted + rounding_bit
  result ← SatQ(rounded, narrow_esize)
  Dd[i] ← result

Example

VQRSHRN.dt d0, q2, #16

Encoding

Binary Layout

111100111

31:23

D

22

11

21:20

size

19:18

10

17:16

Vd

15:12

0

11

010

10:8

op

7:6

M

5

0

4

Vm

3:0

 

Format NEON Shift

Opcode 0xF3B20280

Extension NEON (SIMD)

Operands

• Dd
  Dest Narrow
• Qm
  Src Wide
• imm
  Signed immediate value

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xF2800950	VQRSHRN{<c>}{<q>}.<type><size> <Dd>, <Qm>, #<imm>		A32		1111001 | U | 1 | D | imm6 | Vd | 100 | 1 | 0 | 1 | M | 1 | Vm
0xEF800950	VQRSHRN{<c>}{<q>}.<type><size> <Dd>, <Qm>, #<imm>		T32		111 | U | 11111 | D | imm6 | Vd | 100 | 1 | 0 | 1 | M | 1 | Vm
0xF3B20280	VQRSHRN{<c>}{<q>}.<dt> <Dd>, <Qm>, #0		A32		111100111 | D | 11 | size | 10 | Vd | 0 | 010 | op | M | 0 | Vm
0xFFB20280	VQRSHRN{<c>}{<q>}.<dt> <Dd>, <Qm>, #0		T32		111111111 | D | 11 | size | 10 | Vd | 0 | 010 | op | M | 0 | Vm

Description

Takes each element in a quadword vector of integers, right shifts them by an immediate value, and places the signed rounded results in a doubleword vector