vqrshrn

Vector Saturating Rounding Shift Right Narrow

VQRSHRN<c>.<dt> <Dd>, <Qm>, #<imm>

Shifts right, saturates, rounds, and narrows.

Details

Vector Saturating Rounding Shift Right Narrow shifts each element in Qm right by an immediate value with rounding, saturates to the narrower result type, and packs the narrowed results into Dd. Rounding is applied before truncation and narrowing. This reduces element size by half and narrows the register from 128-bit to 64-bit. All condition flags (N, Z, C, V) remain unaffected. This is an A32/T32 NEON instruction.

Pseudocode Operation

shift_amount ← imm6
for i = 0 to narrow_elements-1 do
  wide_value ← Qm[i]
  rounding_bit ← wide_value[shift_amount-1]
  shifted ← wide_value >> shift_amount
  rounded ← shifted + rounding_bit
  result ← SatQ(rounded, narrow_esize)
  Dd[i] ← result

Example

VQRSHRN.dt d0, q2, #16

Encoding

Binary Layout
111100111
D
11
size
10
Vd
0
010
op
M
0
Vm
 
Format NEON Shift
Opcode 0xF3B20280
Extension NEON (SIMD)

Operands

  • Dd
    Dest Narrow
  • Qm
    Src Wide
  • imm
    Signed immediate value

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2800950 VQRSHRN{<c>}{<q>}.<type><size> <Dd>, <Qm>, #<imm> A32 1111001 | U | 1 | D | imm6 | Vd | 100 | 1 | 0 | 1 | M | 1 | Vm
0xEF800950 VQRSHRN{<c>}{<q>}.<type><size> <Dd>, <Qm>, #<imm> T32 111 | U | 11111 | D | imm6 | Vd | 100 | 1 | 0 | 1 | M | 1 | Vm
0xF3B20280 VQRSHRN{<c>}{<q>}.<dt> <Dd>, <Qm>, #0 A32 111100111 | D | 11 | size | 10 | Vd | 0 | 010 | op | M | 0 | Vm
0xFFB20280 VQRSHRN{<c>}{<q>}.<dt> <Dd>, <Qm>, #0 T32 111111111 | D | 11 | size | 10 | Vd | 0 | 010 | op | M | 0 | Vm

Description

takes each element in a quadword vector of integers, right shifts them by an immediate value, and places the signed rounded results in a doubleword vector