sttrh

Store Register Halfword (Unprivileged)

STTRH <Wt>, [<Xn|SP>, #<simm>]

Stores a halfword as if in EL0.

Details

Stores a halfword from Wt to memory at [Xn + simm] with unprivileged semantics, as if the access were made from EL0. This is an AArch64-only instruction that may be used from higher privilege levels. No condition flags are affected.

Pseudocode Operation

address ← Xn + SignExtend(imm9); [address] ← Wt<15:0>; access performed at EL0 privilege level

Example

STTRH w3, [x1, #-8]

Encoding

Binary Layout
01
111
0
00
00
0
imm9
10
Rn
Rt
 
Format Load/Store
Opcode 0x78000800
Extension Base

Operands

  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register
  • simm
    Signed immediate offset

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x78000800 STTRH <Wt>, [<Xn|SP>{, #<simm>}] A64 01 | 111 | 0 | 00 | 00 | 0 | imm9 | 10 | Rn | Rt

Description

Store Register Halfword (unprivileged) stores a halfword from a 32-bit register to memory. The address that is used for the store is calculated from a base register and an immediate offset. Memory accesses made by the instruction behave as if the instruction was executed at EL0 if the Effective value of PSTATE.UAO is 0 and either: Otherwise, the memory access operates with the restrictions determined by the Exception level at which the instruction is executed. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(16) data;

boolean privileged = AArch64.IsUnprivAccessPriv();
AccessDescriptor accdesc = CreateAccDescGPR(MemOp_STORE, FALSE, privileged, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

address = GenerateAddress(address, offset, accdesc);

data = X[t, 16];
Mem[address, 2, accdesc] = data;