vmovn

Vector Move Narrow

VMOVN<c>.<dt> <Dd>, <Qm>

Copies 2N-bit elements to N-bit elements (Narrowing).

Details

Narrows 2N-bit elements from a 128-bit source register to N-bit elements in a 64-bit destination register, discarding the upper bits. The sz field determines the source element size (16, 32, or 64 bits) and corresponding destination size. Condition flags are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.

Pseudocode Operation

for i = 0 to (128 / source_element_width) - 1:
  Dd[i] ← Qm[i][destination_element_width-1:0]

Example

VMOVN.dt d0, q2

Encoding

Binary Layout
111100111
D
11
size
10
Vd
0
0100
0
M
0
Vm
 
Format NEON 2-Reg
Opcode 0xF3B20200
Extension NEON (SIMD)

Operands

  • Dd
    Dest Narrow
  • Qm
    Src Wide

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3B20200 VMOVN{<c>}{<q>}.<dt> <Dd>, <Qm> A32 111100111 | D | 11 | size | 10 | Vd | 0 | 0100 | 0 | M | 0 | Vm
0xFFB20200 VMOVN{<c>}{<q>}.<dt> <Dd>, <Qm> T32 111111111 | D | 11 | size | 10 | Vd | 0 | 0100 | 0 | M | 0 | Vm

Description

Vector Move and Narrow copies the least significant half of each element of a quadword vector into the corresponding elements of a doubleword vector. The operand vector elements can be any one of 16-bit, 32-bit, or 64-bit integers. There is no distinction between signed and unsigned integers. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for e = 0 to elements-1
        Elem[D[d],e,esize] = Elem[Qin[m>>1],e,2*esize]<esize-1:0>;