extr

Extract

EXTR <Wd>, <Wn>, <Wm>, #<lsb>

Extracts a register from a pair of registers.

Pseudocode Operation

temp ← (Wn[31:0] << 32) | Wm[31:0]
Wd ← temp[(lsb + 31):lsb]

Example

EXTR w0, w1, w2, #0

Encoding

Binary Layout

0

31

00

30:29

100111

28:23

0

22

0

21

Rm

20:16

imms

15:10

Rn

9:5

Rd

4:0

 

Format Data Processing

Opcode 0x13800000

Extension Base

Operands

• Wd
  Destination 32-bit integer register
• Wn
  High
• Wm
  Low
• lsb
  Least-significant bit position

Related

Other forms of extr

• extr Extract (64-bit)

More in Base

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x13800000	EXTR <Wd>, <Wn>, <Wm>, #<lsb>		A64		0 | 00 | 100111 | 0 | 0 | Rm | imms | Rn | Rd
0x93C00000	EXTR <Xd>, <Xn>, <Xm>, #<lsb>		A64		1 | 00 | 100111 | 1 | 0 | Rm | imms | Rn | Rd

Description

Extract register extracts a register from a pair of registers.

Operation

bits(datasize) result;
bits(datasize) operand1 = X[n, datasize];
bits(datasize) operand2 = X[m, datasize];
bits(2*datasize) concat = operand1:operand2;

result = concat<(lsb+datasize)-1:lsb>;

X[d, datasize] = result;