neg

Vector Negate

NEG <Vd>.<T>, <Vn>.<T>

Negates integer elements.

Details

Negates each signed or unsigned integer element in the source vector and stores the result in the destination vector. The operation processes all elements in parallel; Q determines 64-bit (Q=0) or 128-bit (Q=1) operation, and size determines element width (8, 16, 32, or 64 bits). This is a NEON SIMD instruction available in AArch64 only. No condition flags are affected.

Pseudocode Operation

element_size ← 8 << size;
for i = 0 to (vector_length / element_size - 1)
  Vd.<element_size>[i] ← -Vn.<element_size>[i];

Example

NEG v0.4s.T, v1.4s.T

Encoding

Binary Layout
0
Q
1
01110
size
10000
01011
10
Rn
Rd
 
Format SIMD Two Register
Opcode 0x2E20B800
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x7EE0B800 NEG D<d>, D<n> A64 01 | 1 | 11110 | 11 | 10000 | 01011 | 10 | Rn | Rd
0x2E20B800 NEG <Vd>.<T>, <Vn>.<T> A64 0 | Q | 1 | 01110 | size | 10000 | 01011 | 10 | Rn | Rd
0x4B0003E0 NEG <Wd>, <Wm>{, <shift> #<amount>} A64 0 | 1 | 0 | 01011 | shift | 0 | Rm | imm6 | 11111 | Rd
0xCB0003E0 NEG <Xd>, <Xm>{, <shift> #<amount>} A64 1 | 1 | 0 | 01011 | shift | 0 | Rm | imm6 | 11111 | Rd
0x0417A000 NEG <Zd>.<T>, <Pg>/M, <Zn>.<T> A64 00000100 | size | 010 | 11 | 1 | 101 | Pg | Zn | Zd

Description

Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n, datasize];
bits(datasize) result;
integer element;

for e = 0 to elements-1
    element = SInt(Elem[operand, e, esize]);
    if neg then
        element = -element;
    else
        element = Abs(element);
    Elem[result, e, esize] = element<esize-1:0>;

V[d, datasize] = result;