pmull
Polynomial Multiply Long (A64)
Polynomial multiply long (NEON).
Pseudocode Operation
product ← PolynomialMultiply(Vn[0], Vm[0])
Vd ← product[127:0]Example
Encoding
Operands
-
Vd
Destination SIMD/FP vector register -
Vn
First source SIMD/FP vector register -
Vm
Second source SIMD/FP vector register
Reference
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x0E20E000 | PMULL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> | A64 | 0 | Q | 0 | 01110 | size | 1 | Rm | 1110 | 00 | Rn | Rd |
Description
Polynomial Multiply Long. This instruction multiplies corresponding elements in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. For information about multiplying polynomials, see Polynomial arithmetic over {0, 1}. The PMULL instruction extracts each source vector from the lower half of each source register. The PMULL2 instruction extracts each source vector from the upper half of each source register. The PMULL and PMULL2 variants that operate on 64-bit source elements are defined only when FEAT_PMULL is implemented. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Operation
CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part, datasize];
bits(datasize) operand2 = Vpart[m, part, datasize];
bits(2*datasize) result;
bits(esize) element1;
bits(esize) element2;
for e = 0 to elements-1
element1 = Elem[operand1, e, esize];
element2 = Elem[operand2, e, esize];
Elem[result, e, 2*esize] = PolynomialMult(element1, element2);
V[d, 2*datasize] = result;