uadd16

Unsigned Add 16 (A32)

UADD16<c> <Rd>, <Rn>, <Rm>

Parallel add of two unsigned 16-bit halfwords.

Pseudocode Operation

Rd[31:16] ← Rn[31:16] + Rm[31:16]
Rd[15:0] ← Rn[15:0] + Rm[15:0]
GE[3] ← (Rn[31:16] + Rm[31:16] < 2^16) ? 0 : 1
GE[2] ← (Rn[31:16] + Rm[31:16] < 2^16) ? 1 : 0
GE[1] ← (Rn[15:0] + Rm[15:0] < 2^16) ? 0 : 1
GE[0] ← (Rn[15:0] + Rm[15:0] < 2^16) ? 1 : 0

Example

UADD16 r0, r1, r2

Encoding

Binary Layout

cond

31:28

01100

27:23

101

22:20

Rn

19:16

Rd

15:12

1

11

1

10

1

9

1

8

0

7

00

6:5

1

4

Rm

3:0

 

Format SIMD Integer

Opcode 0x06500F10

Extension A32 (DSP)

Operands

• Rd
  Destination general-purpose register
• Rn
  First source / base general-purpose register
• Rm
  Second source / offset general-purpose register

Related

More in A32 (DSP)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x06500F10	UADD16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>		A32		cond | 01100 | 101 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 00 | 1 | Rm
0xFA90F040	UADD16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>		T32		111110101 | 001 | Rn | 1111 | Rd | 0 | 1 | 0 | 0 | Rm

Description

Unsigned Add 16 performs two 16-bit unsigned integer additions, and writes the results to the destination register. It sets PSTATE.GE according to the results of the additions.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    sum1 = UInt(R[n]<15:0>) + UInt(R[m]<15:0>);
    sum2 = UInt(R[n]<31:16>) + UInt(R[m]<31:16>);
    R[d]<15:0>  = sum1<15:0>;
    R[d]<31:16> = sum2<15:0>;
    PSTATE.GE<1:0> = if sum1 >= 0x10000 then '11' else '00';
    PSTATE.GE<3:2> = if sum2 >= 0x10000 then '11' else '00';