sxtb16

Signed Extend Byte 16 (A32)

SXTB16<c> <Rd>, <Rm> {, <rotation>}

Sign-extends two bytes to two halfwords.

Details

Sign-extends the two low bytes (bits 7:0 and 15:8) of Rm to two 16-bit halfwords in Rd, with an optional rotation applied to Rm before extraction. A32 instruction; requires DSP extension. Does not affect PSTATE flags. The condition code suffix controls execution.

Pseudocode Operation

rotated ← ROR(Rm, rotation); Rd<15:0> ← SignExtend(rotated<7:0>, 16); Rd<31:16> ← SignExtend(rotated<15:8>, 16);

Example

SXTB16 r0, r2

Encoding

Binary Layout

cond

01101

1111

rotate

0111

Format Data Proc

Opcode 0x068F0070

Extension A32 (DSP)

Operands

Rd
Destination general-purpose register
Rm
Second source / offset general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x068F0070	SXTB16{<c>}{<q>} {<Rd>,} <Rm> {, ROR #<amount>}		A32		cond \| 01101 \| 0 \| 00 \| 1111 \| Rd \| rotate \| 0 \| 0 \| 0111 \| Rm
0xFA2FF080	SXTB16{<c>}{<q>} {<Rd>,} <Rm> {, ROR #<amount>}		T32		111110100 \| 01 \| 0 \| 1111 \| 1111 \| Rd \| 1 \| 0 \| rotate \| Rm

Description

Signed Extend Byte 16 extracts two 8-bit values from a register, sign-extends them to 16 bits each, and writes the results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    rotated = ROR(R[m], rotation);
    R[d]<15:0>  = SignExtend(rotated<7:0>, 16);
    R[d]<31:16> = SignExtend(rotated<23:16>, 16);