ssbb

Speculative Store Bypass Barrier (A32)

SSBB

Prevents speculative loads bypassing earlier stores (v8.0).

Pseudocode Operation

// Prevent speculative load execution past prior stores
StoreBypassBarrier()
// All prior stores complete before subsequent loads can execute

Encoding

Binary Layout

111101010111

31:20

1

19

1

18

1

17

1

16

1

15

1

14

1

13

1

12

0

11

0

10

0

9

0

8

0100

7:4

0000

3:0

 

Format System Hint

Opcode 0xF57FF040

Extension A32 (v8.0)

Operands

Related

More in A32 (v8.0)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xF57FF040	SSBB{<q>}		A32		111101010111 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0100 | 0000
0xF3BF8F40	SSBB{<q>}		T32		111100111011 | 1 | 1 | 1 | 1 | 10 | 0 | 0 | 1 | 1 | 1 | 1 | 0100 | 0000

Description

Speculative Store Bypass Barrier is a memory barrier which prevents speculative loads from bypassing earlier stores to the same virtual address under certain conditions. The semantics of the Speculative Store Bypass Barrier are:

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    SpeculativeStoreBypassBarrierToVA();