faddv

SVE Floating-Point Add Reduction

FADDV <Vd>, <Pg>, <Zn>.<T>

Sums all active floating-point elements into a scalar result.

Pseudocode Operation

result ← 0.0
for i = 0 to VL/element_size-1:
  if Pg[i] then
    result ← result + Zn[i]
Vd ← result

Example

FADDV v0.4s, p0/m, z1.s.T

Encoding

Binary Layout

01100101

31:24

size

23:22

000

21:19

00

18:17

0

16

001

15:13

Pg

12:10

Zn

9:5

Vd

4:0

 

Format SVE Reduction

Opcode 0x65002000

Extension SVE

Operands

• Vd
  Dest Scalar
• Pg
  Mask
• Zn
  Vector

Related

More in SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x65002000	FADDV <V><d>, <Pg>, <Zn>.<T>		A64		01100101 | size | 000 | 00 | 0 | 001 | Pg | Zn | Vd

Description

Floating-point add horizontally over all lanes of a vector using a recursive pairwise reduction, and place the result in the SIMD&FP scalar destination register. Inactive elements in the source vector are treated as +0.0.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(esize) identity = FPZero('0', esize);

V[d, esize] = FPReducePredicated(ReduceOp_FADD, operand, mask, identity, FPCR);