st1h

SVE Store Contiguous Halfwords

ST1H { <Zt>.H }, <Pg>, [<Xn|SP>]

Stores active halfwords from vector to memory.

Details

Stores active halfwords from a SVE vector register to memory under predicate control. Only elements where the corresponding predicate bit is set are written to addresses [Xn|SP + 2*i]; inactive elements do not generate memory operations. No flags are affected.

Pseudocode Operation

for i = 0 to VL/16-1
  if Pg[i] == 1 then
    [Xn + 2*i] ← Zt.H[i]

Example

ST1H p0/m, [x1]

Encoding

Binary Layout
1110010
0
1
size
0
imm4
111
Pg
Rn
Zt
 
Format SVE Store
Opcode 0xE480E000
Extension SVE

Operands

  • Zt
    Src Vector
  • Pg
    Predicate
  • Xn
    Base Addr

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xA0602000 ST1H { <Zt1>.H-<Zt2>.H }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000000110 | imm4 | 0 | 0 | 1 | PNg | Rn | Zt | 0
0xA060A000 ST1H { <Zt1>.H-<Zt4>.H }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000000110 | imm4 | 1 | 0 | 1 | PNg | Rn | Zt | 0 | 0
0xA0202000 ST1H { <Zt1>.H-<Zt2>.H }, <PNg>, [<Xn|SP>, <Xm>, LSL #1] A64 10100000001 | Rm | 0 | 0 | 1 | PNg | Rn | Zt | 0
0xA020A000 ST1H { <Zt1>.H-<Zt4>.H }, <PNg>, [<Xn|SP>, <Xm>, LSL #1] A64 10100000001 | Rm | 1 | 0 | 1 | PNg | Rn | Zt | 0 | 0
0xA1602000 ST1H { <Zt1>.H, <Zt2>.H }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000010110 | imm4 | 0 | 0 | 1 | PNg | Rn | T | 0 | Zt
0xA160A000 ST1H { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <PNg>, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000010110 | imm4 | 1 | 0 | 1 | PNg | Rn | T | 0 | 0 | Zt
0xA1202000 ST1H { <Zt1>.H, <Zt2>.H }, <PNg>, [<Xn|SP>, <Xm>, LSL #1] A64 10100001001 | Rm | 0 | 0 | 1 | PNg | Rn | T | 0 | Zt
0xA120A000 ST1H { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <PNg>, [<Xn|SP>, <Xm>, LSL #1] A64 10100001001 | Rm | 1 | 0 | 1 | PNg | Rn | T | 0 | 0 | Zt
0xE4E0A000 ST1H { <Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}] A64 1110010 | 0 | 1 | 11 | imm5 | 101 | Pg | Zn | Zt
0xE4C0A000 ST1H { <Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}] A64 1110010 | 0 | 1 | 10 | imm5 | 101 | Pg | Zn | Zt
0xE480E000 ST1H { <Zt>.<T> }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] A64 1110010 | 0 | 1 | size | 0 | imm4 | 111 | Pg | Rn | Zt
0xE4804000 ST1H { <Zt>.<T> }, <Pg>, [<Xn|SP>, <Xm>, LSL #1] A64 1110010 | 01 | size | Rm | 010 | Pg | Rn | Zt
0xE4E08000 ST1H { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #1] A64 1110010 | 0 | 1 | 11 | Zm | 1 | xs | 0 | Pg | Rn | Zt
0xE4A08000 ST1H { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #1] A64 1110010 | 0 | 1 | 01 | Zm | 1 | xs | 0 | Pg | Rn | Zt

Description

Contiguous store of halfwords from elements of a vector register to the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements are not written to memory.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(64) base;
bits(PL) mask = P[g, PL];
bits(VL) src;
constant integer mbytes = msize DIV 8;
boolean contiguous = TRUE;
boolean nontemporal = FALSE;
boolean tagchecked = n != 31;
AccessDescriptor accdesc = CreateAccDescSVE(MemOp_STORE, nontemporal, contiguous, tagchecked);

if !AnyActiveElement(mask, esize) then
    if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then
        CheckSPAlignment();
else
    if n == 31 then CheckSPAlignment();
    base = if n == 31 then SP[] else X[n, 64];
    src = Z[t, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        integer eoff = (offset * elements) + e;
        bits(64) addr = GenerateAddress(base, eoff * mbytes, accdesc);
        Mem[addr, mbytes, accdesc] = Elem[src, e, esize]<msize-1:0>;