mla

Multiply Accumulate (A32)

MLA{S}<c> <Rd>, <Rn>, <Rm>, <Ra>

Calculates Rd = (Rn * Rm) + Ra.

Pseudocode Operation

product ← Rn * Rm
Rd ← product + Ra
if S == 1 then
  N ← Rd[31]
  Z ← (Rd == 0)
  C ← unpredictable
  V ← unpredictable

Example

MLA r0, r1, r2, r5

Encoding

Binary Layout

cond

31:28

0000

27:24

001

23:21

19:16

15:12

11:8

1001

7:4

3:0

Format Multiply

Opcode 0x00200090

Extension A32 (Base)

Operands

Rd
Destination general-purpose register
Rn
First source / base general-purpose register
Rm
Second source / offset general-purpose register
Ra
Addend

Other forms of mla

mla Vector Multiply-Accumulate
mla Multiply Accumulate (Thumb)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x00200090	MLA{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>		A32		cond \| 0000 \| 001 \| 0 \| Rd \| Ra \| Rm \| 1001 \| Rn
0xFB000000	MLA{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>		T32		111110110 \| 000 \| Rn \| Ra \| Rd \| 00 \| 00 \| Rm

Description

Multiply Accumulate multiplies two register values, and adds a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. In an A32 instruction, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many implementations.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    operand1 = SInt(R[n]);  // operand1 = UInt(R[n]) produces the same final results
    operand2 = SInt(R[m]);  // operand2 = UInt(R[m]) produces the same final results
    addend   = SInt(R[a]);  // addend   = UInt(R[a]) produces the same final results
    result = operand1 * operand2 + addend;
    R[d] = result<31:0>;
    if setflags then
        PSTATE.N = result<31>;
        PSTATE.Z = IsZeroBit(result<31:0>);
        // PSTATE.C, PSTATE.V unchanged

mla