miaph

Multiply with Internal Accumulate Packed Halfwords

MIAPH<c> <Acc>, <Rn>, <Rm>

SIMD multiply of packed halfwords to internal acc (XScale Legacy).

Details

Multiply with Internal Accumulate Packed Halfwords performs SIMD multiplication of two packed 16-bit signed halfwords from Rn and Rm, accumulating each product into corresponding 40-bit internal accumulators. This XScale legacy A32 instruction is encoded as a coprocessor operation; condition flags are not updated, and this instruction is deprecated in modern ARM implementations.

Pseudocode Operation

operand1_low ← SignExtend(Rn[15:0], 32);
operand1_high ← SignExtend(Rn[31:16], 32);
operand2_low ← SignExtend(Rm[15:0], 32);
operand2_high ← SignExtend(Rm[31:16], 32);
product_low ← operand1_low * operand2_low;
product_high ← operand1_high * operand2_high;
internalAccumulator[Acc] ← internalAccumulator[Acc] + product_low;
internalAccumulator[Acc+1] ← internalAccumulator[Acc+1] + product_high;

Example

MIAPH Acc, r1, r2

Encoding

Binary Layout
cond
11100010
1000
Rn
Acc
0000
0001
Rm
 
Format Coprocessor
Opcode 0x0E280010
Extension A32 (XScale)

Operands

  • Acc
    Accumulator
  • Rn
    First source / base general-purpose register
  • Rm
    Second source / offset general-purpose register