ldr

Load Register (Immediate)

LDR <Wt>, [<Xn|SP>, #<pimm>]

Loads a word from memory (Immediate offset).

Details

Load Register (Immediate) loads a 32-bit word from memory at an offset address into a 32-bit register. The instruction does not affect the condition flags. It executes in AArch64 state and is available at all privilege levels.

Pseudocode Operation

address ← Xn + (zero_extend(imm12) << 2); Wt ← [address]

Example

LDR w3, [x1, #16]

Encoding

Binary Layout
10
111
0
01
01
imm12
Rn
Rt
 
Format Load/Store Imm
Opcode 0xB9400000
Extension Base

Operands

  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register
  • pimm
    Positive immediate offset

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x3C400400 LDR <Bt>, [<Xn|SP>], #<simm> A64 00 | 111 | 1 | 00 | 01 | 0 | imm9 | 01 | Rn | Rt
0x7C400400 LDR <Ht>, [<Xn|SP>], #<simm> A64 01 | 111 | 1 | 00 | 01 | 0 | imm9 | 01 | Rn | Rt
0xBC400400 LDR <St>, [<Xn|SP>], #<simm> A64 10 | 111 | 1 | 00 | 01 | 0 | imm9 | 01 | Rn | Rt
0xFC400400 LDR <Dt>, [<Xn|SP>], #<simm> A64 11 | 111 | 1 | 00 | 01 | 0 | imm9 | 01 | Rn | Rt
0x3CC00400 LDR <Qt>, [<Xn|SP>], #<simm> A64 00 | 111 | 1 | 00 | 11 | 0 | imm9 | 01 | Rn | Rt
0x3C400C00 LDR <Bt>, [<Xn|SP>, #<simm>]! A64 00 | 111 | 1 | 00 | 01 | 0 | imm9 | 11 | Rn | Rt
0x7C400C00 LDR <Ht>, [<Xn|SP>, #<simm>]! A64 01 | 111 | 1 | 00 | 01 | 0 | imm9 | 11 | Rn | Rt
0xBC400C00 LDR <St>, [<Xn|SP>, #<simm>]! A64 10 | 111 | 1 | 00 | 01 | 0 | imm9 | 11 | Rn | Rt
0xFC400C00 LDR <Dt>, [<Xn|SP>, #<simm>]! A64 11 | 111 | 1 | 00 | 01 | 0 | imm9 | 11 | Rn | Rt
0x3CC00C00 LDR <Qt>, [<Xn|SP>, #<simm>]! A64 00 | 111 | 1 | 00 | 11 | 0 | imm9 | 11 | Rn | Rt
0x3D400000 LDR <Bt>, [<Xn|SP>{, #<pimm>}] A64 00 | 111 | 1 | 01 | 01 | imm12 | Rn | Rt
0x7D400000 LDR <Ht>, [<Xn|SP>{, #<pimm>}] A64 01 | 111 | 1 | 01 | 01 | imm12 | Rn | Rt
0xBD400000 LDR <St>, [<Xn|SP>{, #<pimm>}] A64 10 | 111 | 1 | 01 | 01 | imm12 | Rn | Rt
0xFD400000 LDR <Dt>, [<Xn|SP>{, #<pimm>}] A64 11 | 111 | 1 | 01 | 01 | imm12 | Rn | Rt

Description

Load Register (immediate) loads a word or doubleword from memory and writes it to a register. The address that is used for the load is calculated from a base register and an immediate offset. For information about memory accesses, see Load/Store addressing modes. The Unsigned offset variant scales the immediate offset value by the size of the value accessed before adding it to the base register value.

Operation

bits(64) address;
bits(datasize) data;

boolean privileged = PSTATE.EL != EL0;
AccessDescriptor accdesc = CreateAccDescGPR(MemOp_LOAD, FALSE, privileged, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

if !postindex then
    address = GenerateAddress(address, offset, accdesc);

data = Mem[address, datasize DIV 8, accdesc];
X[t, regsize] = ZeroExtend(data, regsize);

if wback then
    if wb_unknown then
        address = bits(64) UNKNOWN;
    elsif postindex then
        address = GenerateAddress(address, offset, accdesc);
    if n == 31 then
        SP[] = address;
    else
        X[n, 64] = address;