casa

Compare and Swap Word (Acquire)

CASA <Ws>, <Wt>, [<Xn|SP>]

Atomic CAS with Acquire semantics.

Details

Atomic compare and swap of a 32-bit word with acquire semantics. Compares Ws with memory at address Xn; if equal, stores Wt and loads old value into Ws; otherwise loads the memory value into Ws. This AArch64-only LSE instruction provides an acquire barrier for load operations, preventing subsequent memory operations from being observed before this load completes. Condition flags are not affected.

Pseudocode Operation

address ← Xn; AcquireSemantics(); old_value ← [address]; if Ws == old_value then [address] ← Wt; Ws ← old_value; else Ws ← old_value;

Example

CASA w6, w3, [x1]

Encoding

Binary Layout
10
0010001
1
1
Rs
0
11111
Rn
Rt
 
Format Atomic
Opcode 0x88E07C00
Extension LSE (Atomics)

Operands

  • Ws
    Compare
  • Wt
    Swap
  • Xn
    First source / base 64-bit integer register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x88E07C00 CASA <Ws>, <Wt>, [<Xn|SP>{, #0}] A64 10 | 0010001 | 1 | 1 | Rs | 0 | 11111 | Rn | Rt
0xC8E07C00 CASA <Xs>, <Xt>, [<Xn|SP>{, #0}] A64 11 | 0010001 | 1 | 1 | Rs | 0 | 11111 | Rn | Rt

Description

Compare and Swap word or doubleword in memory reads a 32-bit word or 64-bit doubleword from memory, and compares it against the value held in a first register. If the comparison is equal, the value in a second register is written to memory. If the write is performed, the read and write occur atomically such that no other modification of the memory location can take place between the read and write. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about memory accesses, see Load/Store addressing modes. The architecture permits that the data read clears any exclusive monitors associated with that location, even if the compare subsequently fails. If the instruction generates a synchronous Data Abort, the register which is compared and loaded, that is <Ws>, or <Xs>, is restored to the value held in the register before the instruction was executed.

Operation

bits(64) address;
bits(datasize) comparevalue;
bits(datasize) newvalue;
bits(datasize) data;

AccessDescriptor accdesc = CreateAccDescAtomicOp(MemAtomicOp_CAS, acquire, release, tagchecked);

comparevalue = X[s, datasize];
newvalue = X[t, datasize];

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

data = MemAtomic(address, comparevalue, newvalue, accdesc);

X[s, regsize] = ZeroExtend(data, regsize);