st64bv

Single-copy Atomic 64-byte Store with Return

ST64BV <Ws>, <Xt>, [<Xn|SP>]

Stores 64 bytes atomically and returns status (Success/Fail).

Pseudocode Operation

address ← Xn|SP; if address<5:0> != 0 then Fault(Alignment); success ← AtomicStore64B(address, [Xt, Xt+1, ..., Xt+7]); Ws ← if success then 0 else implementation_defined_nonzero;

Example

ST64BV w6, x3, [x1]

Encoding

Binary Layout

11

31:30

111

29:27

0

26

00

25:24

0

23

0

22

1

21

Rs

20:16

1

15

011

14:12

00

11:10

Rn

9:5

Rt

4:0

 

Format Load/Store

Opcode 0xF820B000

Extension LSE (Atomics)

Operands

• Ws
  Status Dest
• Xt
  Data Src
• Xn
  First source / base 64-bit integer register

Related

More in LSE (Atomics)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xF820B000	ST64BV <Xs>, <Xt>, [<Xn|SP>]		A64		11 | 111 | 0 | 00 | 0 | 0 | 1 | Rs | 1 | 011 | 00 | Rn | Rt

Description

Single-copy Atomic 64-byte Store with status result stores eight 64-bit doublewords from consecutive registers, Xt to X(t+7), to a memory location, and writes the status result of the store to a register. The data that is stored is atomic and is required to be 64-byte aligned.

Operation

CheckST64BVEnabled();

bits(512) data;
bits(64) address;
bits(64) value;
bits(64) status;

AccessDescriptor accdesc = CreateAccDescLS64(memop, tagchecked);
for i = 0 to 7
    value = X[t+i, 64];
    if BigEndian(accdesc.acctype) then value = BigEndianReverse(value);
    data<63+64*i:64*i> = value;

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

status = MemStore64BWithRet(address, data, accdesc);

if s != 31 then X[s, 64] = status;