st64bv

Single-copy Atomic 64-byte Store with Return

ST64BV <Ws>, <Xt>, [<Xn|SP>]

Stores 64 bytes atomically and returns status (Success/Fail).

Details

Single-copy Atomic 64-byte Store with Return writes a 64-byte block from 8 consecutive X-registers starting at Xt to memory and returns a status value in Ws indicating success (0) or failure (non-zero). The store is atomic; on failure, memory is not modified and Ws is written with a non-zero value. Address must be 64-byte aligned. Condition flags are not affected. Execution is AArch64-only (FEAT_LS64).

Pseudocode Operation

address ← Xn|SP; if address<5:0> != 0 then Fault(Alignment); success ← AtomicStore64B(address, [Xt, Xt+1, ..., Xt+7]); Ws ← if success then 0 else implementation_defined_nonzero;

Example

ST64BV w6, x3, [x1]

Encoding

Binary Layout
11
111
0
00
0
0
1
Rs
1
011
00
Rn
Rt
 
Format Load/Store
Opcode 0xF820B000
Extension LSE (Atomics)

Operands

  • Ws
    Status Dest
  • Xt
    Data Src
  • Xn
    First source / base 64-bit integer register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF820B000 ST64BV <Xs>, <Xt>, [<Xn|SP>] A64 11 | 111 | 0 | 00 | 0 | 0 | 1 | Rs | 1 | 011 | 00 | Rn | Rt

Description

Single-copy Atomic 64-byte Store with status result stores eight 64-bit doublewords from consecutive registers, Xt to X(t+7), to a memory location, and writes the status result of the store to a register. The data that is stored is atomic and is required to be 64-byte aligned.

Operation

CheckST64BVEnabled();

bits(512) data;
bits(64) address;
bits(64) value;
bits(64) status;

AccessDescriptor accdesc = CreateAccDescLS64(memop, tagchecked);
for i = 0 to 7
    value = X[t+i, 64];
    if BigEndian(accdesc.acctype) then value = BigEndianReverse(value);
    data<63+64*i:64*i> = value;

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

status = MemStore64BWithRet(address, data, accdesc);

if s != 31 then X[s, 64] = status;