whilelt
SVE While Less Than
WHILELT <Pd>.<T>, <Xn>, <Xm>
Generates a predicate based on a loop counter (while Xn < Xm).
Details
Generates a predicate register by comparing a loop counter with a limit, setting each element to true if counter < limit. Operates on 64-bit signed integers and generates a predicate for elements of type T (8-bit, 16-bit, 32-bit, or 64-bit). No flags are affected. This is an AArch64-only SVE instruction.
Pseudocode Operation
for i = 0 to VL/esize-1
Pd[i] ← (Xn < Xm)
Example
WHILELT p0.T, x1, x2
Encoding
Binary Layout
00100101
size
1
Rm
000
sf
0
1
Rn
0
Pd
Operands
-
Pd
Destination predicate register (SVE) -
Xn
Start -
Xm
Limit
Reference (Arm A64 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x25200400 | WHILELT <Pd>.<T>, <R><n>, <R><m> | A64 | 00100101 | size | 1 | Rm | 000 | sf | 0 | 1 | Rn | 0 | Pd | ||
| 0x25204410 | WHILELT <PNd>.<T>, <Xn>, <Xm>, <vl> | A64 | 00100101 | size | 1 | Rm | 01 | vl | 0 | 0 | 1 | Rn | 1 | 0 | PNd | ||
| 0x25205410 | WHILELT { <Pd1>.<T>, <Pd2>.<T> }, <Xn>, <Xm> | A64 | 00100101 | size | 1 | Rm | 0101 | 0 | 1 | Rn | 1 | Pd | 0 |
Description
Generate a predicate that starting from the lowest numbered element is true while the incrementing value of the first, signed scalar operand is less than the second scalar operand and false thereafter up to the highest numbered element.
The full width of the scalar operands is significant for the purposes of comparison, and the full width first operand is incremented by one for each destination predicate element, irrespective of the predicate result element size. The first general-purpose source register is not itself updated.
The predicate result is placed in the predicate destination register. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.
Operation
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = Ones(PL);
bits(rsize) operand1 = X[n, rsize];
bits(rsize) operand2 = X[m, rsize];
bits(PL) result;
boolean last = TRUE;
constant integer psize = esize DIV 8;
for e = 0 to elements-1
boolean cond;
case op of
when Cmp_LT cond = (Int(operand1, unsigned) < Int(operand2, unsigned));
when Cmp_LE cond = (Int(operand1, unsigned) <= Int(operand2, unsigned));
last = last && cond;
bit pbit = if last then '1' else '0';
Elem[result, e, psize] = ZeroExtend(pbit, psize);
operand1 = operand1 + 1;
PSTATE.<N,Z,C,V> = PredTest(mask, result, esize);
P[d, PL] = result;