usdot
Unsigned Signed Dot Product (A32)
USDOT<c>.S8 <Qd>, <Qn>, <Qm>
Dot product of unsigned and signed integers.
Pseudocode Operation
for i in [0, 1, 2, 3]:
Qd[i*32+31:i*32] ← Qd[i*32+31:i*32] + USSignedDotProduct(UnsignedQn[i*32+31:i*32], SignedQm[i*32+31:i*32])Example
USDOT.S8 q0, q1, q2
Encoding
Binary Layout
01000100
31:24
1
23
0
22
0
21
Zm
20:16
011110
15:10
Zn
9:5
Zda
4:0
Operands
-
Qd
Destination 128-bit SIMD register -
Qn
Unsigned -
Qm
Signed
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x0F80F000 | USDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.4B[<index>] | A64 | 0 | Q | 0 | 01111 | 1 | 0 | L | M | Rm | 1111 | H | 0 | Rn | Rd | ||
| 0x0E809C00 | USDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> | A64 | 0 | Q | 0 | 01110 | 10 | 0 | Rm | 1 | 0011 | 1 | Rn | Rd | ||
| 0x44807800 | USDOT <Zda>.S, <Zn>.B, <Zm>.B | A64 | 01000100 | 1 | 0 | 0 | Zm | 011110 | Zn | Zda | ||
| 0x44A01800 | USDOT <Zda>.S, <Zn>.B, <Zm>.B[<imm>] | A64 | 01000100 | 1 | 0 | 1 | i2 | Zm | 00011 | 0 | Zn | Zda | ||
| 0xC1501028 | USDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] | A64 | 110000010101 | Zm | 0 | Rv | 1 | i2 | Zn | 1 | 0 | 1 | off3 | ||
| 0xC1509028 | USDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>] | A64 | 110000010101 | Zm | 1 | Rv | 1 | i2 | Zn | 0 | 1 | 0 | 1 | off3 | ||
| 0xC1201408 | USDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B | A64 | 11 | 0000010010 | Zm | 0 | Rv | 101 | Zn | 0 | 1 | off3 | ||
| 0xC1301408 | USDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B | A64 | 11 | 0000010011 | Zm | 0 | Rv | 101 | Zn | 0 | 1 | off3 | ||
| 0xC1A01408 | USDOT ZA.S[<Wv>, <offs>{, VGx2}], { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B } | A64 | 11 | 000001101 | Zm | 00 | Rv | 101 | Zn | 00 | 1 | off3 | ||
| 0xC1A11408 | USDOT ZA.S[<Wv>, <offs>{, VGx4}], { <Zn1>.B-<Zn4>.B }, { <Zm1>.B-<Zm4>.B } | A64 | 11 | 000001101 | Zm | 010 | Rv | 101 | Zn | 000 | 1 | off3 |
Description
The unsigned by signed integer dot product instruction computes the dot product of a group of four unsigned 8-bit integer values held in each 32-bit element of the first source vector multiplied by a group of four signed 8-bit integer values in the corresponding 32-bit element of the second source vector, and then destructively adds the widened dot product to the corresponding 32-bit element of the destination vector. This instruction is unpredicated. ID_AA64ZFR0_EL1.I8MM indicates whether this instruction is implemented.
Operation
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(VL) operand1 = Z[n, VL];
bits(VL) operand2 = Z[m, VL];
bits(VL) operand3 = Z[da, VL];
bits(VL) result;
for e = 0 to elements-1
bits(esize) res = Elem[operand3, e, esize];
for i = 0 to 3
integer element1 = UInt(Elem[operand1, 4 * e + i, esize DIV 4]);
integer element2 = SInt(Elem[operand2, 4 * e + i, esize DIV 4]);
res = res + element1 * element2;
Elem[result, e, esize] = res;
Z[da, VL] = result;