vst4

Vector Store Multiple (4-Element Structure)

VST4<c>.<size> <list>, [<Rn>]{!}

Interleaves and stores four registers into memory (e.g., RGBA).

Pseudocode Operation

address ← Rn
for i = 0 to 7 do
  element_size_bits ← size_in_bits(size)
  [address + (i * element_size_bits / 8)] ← Vd[i]
  [address + (i * element_size_bits / 8) + (element_size_bits / 8)] ← Vd+1[i]
  [address + (i * element_size_bits / 8) + (2 * element_size_bits / 8)] ← Vd+2[i]
  [address + (i * element_size_bits / 8) + (3 * element_size_bits / 8)] ← Vd+3[i]
if (writeback) then
  Rn ← Rn + (4 * 8 * element_size_bits / 8)

Example

VST4.size {r0-r3}, [r1]!

Encoding

Binary Layout
111101000
31:23
D
22
0
21
0
20
Rn
19:16
Vd
15:12
itype
11:8
size
7:6
align
5:4
Rm
3:0
 
Format NEON Store
Opcode 0xF4000000
Extension NEON (SIMD)

Operands

  • list
    Src Registers
  • Rn
    First source / base general-purpose register

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF480030F VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] A32 111101001 | D | 0 | 0 | Rn | Vd | 00 | 11 | index_align | 1111
0xF480030D VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! A32 111101001 | D | 0 | 0 | Rn | Vd | 00 | 11 | index_align | 1101
0xF4800300 VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> A32 111101001 | D | 0 | 0 | Rn | Vd | 00 | 11 | index_align | Rm
0xF480070F VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] A32 111101001 | D | 0 | 0 | Rn | Vd | 01 | 11 | index_align | 1111
0xF480070D VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! A32 111101001 | D | 0 | 0 | Rn | Vd | 01 | 11 | index_align | 1101
0xF4800700 VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> A32 111101001 | D | 0 | 0 | Rn | Vd | 01 | 11 | index_align | Rm
0xF4800B0F VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] A32 111101001 | D | 0 | 0 | Rn | Vd | 10 | 11 | index_align | 1111
0xF4800B0D VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! A32 111101001 | D | 0 | 0 | Rn | Vd | 10 | 11 | index_align | 1101
0xF4800B00 VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> A32 111101001 | D | 0 | 0 | Rn | Vd | 10 | 11 | index_align | Rm
0xF980030F VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] T32 111110011 | D | 0 | 0 | Rn | Vd | 00 | 11 | index_align | 1111
0xF980030D VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! T32 111110011 | D | 0 | 0 | Rn | Vd | 00 | 11 | index_align | 1101
0xF9800300 VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> T32 111110011 | D | 0 | 0 | Rn | Vd | 00 | 11 | index_align | Rm
0xF980070F VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] T32 111110011 | D | 0 | 0 | Rn | Vd | 01 | 11 | index_align | 1111
0xF980070D VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! T32 111110011 | D | 0 | 0 | Rn | Vd | 01 | 11 | index_align | 1101

Description

Store multiple 4-element structures from four registers stores multiple 4-element structures to memory from four registers, with interleaving. For more information, see Element and structure load/store instructions. Every element of each register is saved. For details of the addressing mode, see Advanced SIMD addressing mode. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    CheckAdvSIMDEnabled();

    address = R[n];

    boolean nontemporal = FALSE;
    boolean tagchecked  = FALSE;
    AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_STORE, nontemporal, tagchecked);
    if !IsAligned(address, alignment) then
        AArch32.Abort(address, AlignmentFault(accdesc));

    for e = 0 to elements-1
        MemU[address,         ebytes] = Elem[D[d], e,8*ebytes];
        MemU[address+ebytes,  ebytes] = Elem[D[d2],e,8*ebytes];
        MemU[address+2*ebytes,ebytes] = Elem[D[d3],e,8*ebytes];
        MemU[address+3*ebytes,ebytes] = Elem[D[d4],e,8*ebytes];
        address = address + 4*ebytes;
    if wback then
        if register_index then
            R[n] = R[n] + R[m];
        else
            R[n] = R[n] + 32;