bfcvtn

BFloat16 Convert Narrow (NEON)

BFCVTN <Vd>.<Tb>, <Vn>.<Ta>

Converts Float32 to BFloat16 (Lower Half).

Pseudocode Operation

for i = 0 to 3 do
  Vd[i] ← F32_to_BF16(Vn[i])
end for
Vd[8:4] ← Vd[8:4]  // Upper half unchanged

Example

BFCVTN v0.4s.Tb, v1.4s.Ta

Encoding

Binary Layout

01110

28:24

23:22

10000

21:17

10110

16:12

11:10

9:5

4:0

Format NEON 2-Reg

Opcode 0x0EA16800

Extension FEAT_BF16 (AI)

Operands

Vd
Dest (BF16)
Vn
Src (F32)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x0EA16800	BFCVTN{2} <Vd>.<Ta>, <Vn>.4S	A64	0 \| Q \| 0 \| 01110 \| 10 \| 10000 \| 10110 \| 10 \| Rn \| Rd
0x650A3800	BFCVTN <Zd>.B, { <Zn1>.H-<Zn2>.H }	A64	01100101000010100011 \| 1 \| 0 \| Zn \| 0 \| Zd
0xC160E020	BFCVTN <Zd>.H, { <Zn1>.S-<Zn2>.S }	A64	110000010 \| 1 \| 100000111000 \| Zn \| 1 \| Zd

Description

Floating-point convert from single-precision to BFloat16 format (vector) reads each single-precision element in the SIMD&FP source vector, converts each value to BFloat16 format, and writes the results in the lower or upper half of the SIMD&FP destination vector. The result elements are half the width of the source elements. The BFCVTN instruction writes the half-width results to the lower half of the destination vector and clears the upper half to zero, while the BFCVTN2 instruction writes the results to the upper half of the destination vector without affecting the other bits in the register.

Operation

CheckFPAdvSIMDEnabled64();
bits(128) operand = V[n, 128];
bits(64) result;

for e = 0 to elements-1
    Elem[result, e, 16] = FPConvertBF(Elem[operand, e, 32], FPCR);

Vpart[d, part, 64] = result;