ands

Bitwise AND and Set Flags (Immediate)

ANDS <Wd>, <Wn>, #<imm>

Bitwise AND immediate, updates flags.

Pseudocode Operation

result ← Wn AND imm
Wd ← result
N ← result[31]
Z ← (result == 0)
C ← 0
V ← 0

Example

ANDS w0, w1, #16

Encoding

Binary Layout

0

31

11

30:29

100100

28:23

0

22

immr

21:16

imms

15:10

Rn

9:5

Rd

4:0

 

Format Logical (Immediate)

Opcode 0x72000000

Extension Base

Operands

• Wd
  Destination 32-bit integer register
• Wn
  First source / base 32-bit integer register
• imm
  Imm

Related

Other forms of ands

• ands Bitwise AND and Set Flags (Immediate 64-bit)
• ands Bitwise AND and Set Flags (Shifted Register)
• ands Bitwise AND and Set Flags (Shifted Register 64-bit)

More in Base

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x72000000	ANDS <Wd>, <Wn>, #<imm>		A64		0 | 11 | 100100 | 0 | immr | imms | Rn | Rd
0xF2000000	ANDS <Xd>, <Xn>, #<imm>		A64		1 | 11 | 100100 | N | immr | imms | Rn | Rd
0x6A000000	ANDS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}		A64		0 | 11 | 01010 | shift | 0 | Rm | imm6 | Rn | Rd
0xEA000000	ANDS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}		A64		1 | 11 | 01010 | shift | 0 | Rm | imm6 | Rn | Rd
0x25404000	ANDS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B		A64		00100101 | 0 | 1 | 00 | Pm | 01 | Pg | 0 | Pn | 0 | Pd

Description

Bitwise AND (immediate), setting flags, performs a bitwise AND of a register value and an immediate value, and writes the result to the destination register. It updates the condition flags based on the result.

Operation

bits(datasize) result;
bits(datasize) operand1 = X[n, datasize];

result = operand1 AND imm;
PSTATE.<N,Z,C,V> = result<datasize-1>:IsZeroBit(result):'00';

X[d, datasize] = result;