and

Bitwise AND (Shifted Register)

AND <Wd>, <Wn>, <Wm> {, <shift> #<amount>}

Bitwise AND with shifted register.

Details

The Bitwise AND instruction bitwise AND with shifted register.

Pseudocode Operation

Wd ← Wn AND Wm

Example

AND w0, w1, w2

Encoding

Binary Layout
00001010
00
Rm
imm6
Rn
Rd
 
Format Logical (Register)
Opcode 0x0A000000
Extension Base

Operands

  • Wd
    Destination 32-bit integer register
  • Wn
    First source / base 32-bit integer register
  • Wm
    Second source / offset 32-bit integer register