clastb

SVE Conditional Last Element Before

CLASTB <Rdn>, <Pg>, <Rdn>, <Zm>.<T>

Extracts the last active element.

Pseudocode Operation

activecount ← CountActiveLanes(Pg, esize)
if activecount > 0 then
  Rdn ← Zm[activecount - 1]
else
  Rdn ← Rdn

Example

CLASTB r0, p0/m, r0, z2.s.T

Encoding

Binary Layout

00000101

31:24

size

23:22

11000

21:17

101

15:13

12:10

9:5

Rdn

4:0

Format SVE Extract

Opcode 0x0531A000

Extension SVE

Operands

Rdn
Dest/Fallback
Pg
Predicate
Zm
Vector

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x0531A000	CLASTB <R><dn>, <Pg>, <R><dn>, <Zm>.<T>	A64	00000101 \| size \| 11000 \| 1 \| 101 \| Pg \| Zm \| Rdn
0x052B8000	CLASTB <V><dn>, <Pg>, <V><dn>, <Zm>.<T>	A64	00000101 \| size \| 10101 \| 1 \| 100 \| Pg \| Zm \| Vdn
0x05298000	CLASTB <Zdn>.<T>, <Pg>, <Zdn>.<T>, <Zm>.<T>	A64	00000101 \| size \| 10100 \| 1 \| 100 \| Pg \| Zm \| Zdn

Description

From the source vector register extract the last active element, and then zero-extend that element to destructively place in the destination and first source general-purpose register. If there are no active elements then destructively zero-extend the least significant element-size bits of the destination and first source general-purpose register.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(esize) operand1 = X[dn, esize];
bits(VL) operand2 = Z[m, VL];
bits(csize) result;
integer last = LastActiveElement(mask, esize);

if last < 0 then
    result = ZeroExtend(operand1, csize);
else
    if !isBefore then
        last = last + 1;
        if last >= elements then last = 0;
    result = ZeroExtend(Elem[operand2, last, esize], csize);

X[dn, csize] = result;