vbic

Vector Bitwise Bit Clear

VBIC<c> <Qd>, <Qn>, <Qm>

ANDs Vd with NOT of Vm (Vd & ~Vm).

Details

Performs bitwise AND of the first operand with the bitwise NOT of the second operand (Qd ← Qn AND NOT Qm), storing the result in the destination register. This clears bits in Qn where the corresponding bits in Qm are set. No flags are affected.

Pseudocode Operation

Qd ← Qn AND (NOT Qm)

Example

VBIC q0, q1, q2

Encoding

Binary Layout
1111001
0
0
D
01
Vn
Vd
0001
N
0
M
1
Vm
 
Format NEON 3-Reg
Opcode 0xF2100110
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2800130 VBIC{<c>}{<q>}.I32 {<Dd>,} <Dd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 0 | 1 | 1 | imm4
0xF2800170 VBIC{<c>}{<q>}.I32 {<Qd>,} <Qd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 1 | 1 | 1 | imm4
0xF2800930 VBIC{<c>}{<q>}.I16 {<Dd>,} <Dd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 0 | 1 | 1 | imm4
0xF2800970 VBIC{<c>}{<q>}.I16 {<Qd>,} <Qd>, #<imm> A32 1111001 | i | 1 | D | 000 | imm3 | Vd | cmode | 0 | 1 | 1 | 1 | imm4
0xEF800130 VBIC{<c>}{<q>}.I32 {<Dd>,} <Dd>, #<imm> T32 111 | i | 11111 | D | 000 | imm3 | Vd | cmode | 0 | 0 | 1 | 1 | imm4
0xEF800170 VBIC{<c>}{<q>}.I32 {<Qd>,} <Qd>, #<imm> T32 111 | i | 11111 | D | 000 | imm3 | Vd | cmode | 0 | 1 | 1 | 1 | imm4
0xEF800930 VBIC{<c>}{<q>}.I16 {<Dd>,} <Dd>, #<imm> T32 111 | i | 11111 | D | 000 | imm3 | Vd | cmode | 0 | 0 | 1 | 1 | imm4
0xEF800970 VBIC{<c>}{<q>}.I16 {<Qd>,} <Qd>, #<imm> T32 111 | i | 11111 | D | 000 | imm3 | Vd | cmode | 0 | 1 | 1 | 1 | imm4
0xF2100110 VBIC{<c>}{<q>}{.<dt>} {<Dd>,} <Dn>, <Dm> A32 1111001 | 0 | 0 | D | 01 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm
0xF2100150 VBIC{<c>}{<q>}{.<dt>} {<Qd>,} <Qn>, <Qm> A32 1111001 | 0 | 0 | D | 01 | Vn | Vd | 0001 | N | 1 | M | 1 | Vm
0xEF100110 VBIC{<c>}{<q>}{.<dt>} {<Dd>,} <Dn>, <Dm> T32 111 | 0 | 11110 | D | 01 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm
0xEF100150 VBIC{<c>}{<q>}{.<dt>} {<Qd>,} <Qn>, <Qm> T32 111 | 0 | 11110 | D | 01 | Vn | Vd | 0001 | N | 1 | M | 1 | Vm

Description

Vector Bitwise Bit Clear (register) performs a bitwise AND between a register value and the complement of a register value, and places the result in the destination register. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        D[d+r] = D[n+r] AND NOT(D[m+r]);