vcadd

Vector Complex Add (A32)

VCADD<c>.I<size> <Qd>, <Qn>, <Qm>, #<rot>

Complex integer addition with rotation (NEON).

Details

Performs complex addition on pairs of elements within 128-bit SIMD registers, treating each pair as a complex number (real, imaginary), with rotation applied before addition. The rotation is either 90° or 270° as specified by rot. Operates on 32-bit or 64-bit element pairs. NEON extension; no condition flags affected.

Pseudocode Operation

rotation_angle ← if rot == 0 then 90 else 270
for i = 0 to elements_per_128bit_register/2 - 1 do
  real_n ← Qn[2*i]
  imag_n ← Qn[2*i+1]
  real_m ← Qm[2*i]
  imag_m ← Qm[2*i+1]
  rotated_real ← rotate(real_m, imag_m, rotation_angle).real
  rotated_imag ← rotate(real_m, imag_m, rotation_angle).imag
  Qd[2*i] ← real_n + rotated_real
  Qd[2*i+1] ← imag_n + rotated_imag

Example

VCADD.Isize q0, q1, q2, #rot

Encoding

Binary Layout
1111110
rot
1
D
0
S
Vn
Vd
1
0
0
0
N
1
M
0
Vm
 
Format NEON Complex
Opcode 0xFC800840
Extension NEON (Complex)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register
  • rot
    Rot

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xFC800800 VCADD{<q>}.<dt> <Dd>, <Dn>, <Dm>, #<rotate> A32 1111110 | rot | 1 | D | 0 | S | Vn | Vd | 1 | 0 | 0 | 0 | N | 0 | M | 0 | Vm
0xFC800840 VCADD{<q>}.<dt> <Qd>, <Qn>, <Qm>, #<rotate> A32 1111110 | rot | 1 | D | 0 | S | Vn | Vd | 1 | 0 | 0 | 0 | N | 1 | M | 0 | Vm

Description

Vector Complex Add. This instruction operates on complex numbers that are represented in SIMD&FP registers as pairs of elements, with the more significant element holding the imaginary part of the number and the less significant element holding the real part of the number. Each element holds a floating-point value. It performs the following computation on the corresponding complex number element pairs from the two source registers: Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

EncodingSpecificOperations();
CheckAdvSIMDEnabled();
for r = 0 to regs-1
    operand1 = D[n+r];
    operand2 = D[m+r];
    for e = 0 to (elements DIV 2)-1
        bits(esize) element1;
        bits(esize) element3;
        case rot of
            when '0'
                element1 = FPNeg(Elem[operand2,e*2+1,esize]);
                element3 = Elem[operand2,e*2,esize];
            when '1'
                element1 = Elem[operand2,e*2+1,esize];
                element3 = FPNeg(Elem[operand2,e*2,esize]);
        result1 = FPAdd(Elem[operand1,e*2,esize],element1,StandardFPSCRValue());
        result2 = FPAdd(Elem[operand1,e*2+1,esize],element3,StandardFPSCRValue());
        Elem[D[d+r],e*2,esize] = result1;
        Elem[D[d+r],e*2+1,esize] = result2;