frecps

Vector Floating-Point Reciprocal Step

FRECPS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Newton-Raphson step for reciprocal refinement.

Pseudocode Operation

if sz == 0 then
  for i = 0 to elements_in_vector - 1:
    Vd[i] ← 2.0 - (Vn[i] * Vm[i])  // 32-bit float
else
  for i = 0 to elements_in_vector - 1:
    Vd[i] ← 2.0 - (Vn[i] * Vm[i])  // 64-bit float

Example

FRECPS v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout

0

31

Q

30

0

29

011100

28:23

sz

22

1

21

Rm

20:16

11111

15:11

1

10

Rn

9:5

Rd

4:0

 

Format SIMD Three Register

Opcode 0x0E20FC00

Extension NEON (SIMD)

Operands

• Vd
  Destination SIMD/FP vector register
• Vn
  First source SIMD/FP vector register
• Vm
  Second source SIMD/FP vector register

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x5E403C00	FRECPS <Hd>, <Hn>, <Hm>		A64		01 | 0 | 11110 | 0 | 10 | Rm | 00 | 111 | 1 | Rn | Rd
0x5E20FC00	FRECPS <V><d>, <V><n>, <V><m>		A64		01 | 0 | 111100 | sz | 1 | Rm | 11111 | 1 | Rn | Rd
0x0E403C00	FRECPS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>		A64		0 | Q | 0 | 01110 | 0 | 10 | Rm | 00 | 111 | 1 | Rn | Rd
0x0E20FC00	FRECPS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>		A64		0 | Q | 0 | 011100 | sz | 1 | Rm | 11111 | 1 | Rn | Rd
0x65001800	FRECPS <Zd>.<T>, <Zn>.<T>, <Zm>.<T>		A64		01100101 | size | 0 | Zm | 000 | 11 | 0 | Zn | Zd

Description

Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

if elements == 1 then
    CheckFPEnabled64();
else
    CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];

bits(esize) element1;
bits(esize) element2;
boolean merge = elements == 1 && IsMerging(FPCR);
bits(128) result = if merge then V[n, 128] else Zeros(128);

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPRecipStepFused(element1, element2, FPCR);

V[d, 128] = result;