ld1w

SVE Load Contiguous Words

LD1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>]

Loads words from memory into a vector under predicate control.

Details

Loads contiguous words from memory into a SVE vector register under predicate control. Each active predicate element loads one 32-bit value from the address sequence [Xn|SP + 4*i], zero-extending to fill the word element. Inactive elements are zeroed (Z suffix semantics). No flags are affected.

Pseudocode Operation

for i = 0 to VL/32-1
  if Pg[i] == 1 then
    Zt.S[i] ← [Xn + 4*i]
  else
    Zt.S[i] ← 0

Example

LD1W p0/m/Z, [x1]

Encoding

Binary Layout
1010010
101
0
0
imm4
101
Pg
Rn
Zt
 
Format SVE Load
Opcode 0xA540A000
Extension SVE

Operands

  • Zt
    Dest Vector
  • Pg
    Predicate
  • Xn
    Base Addr

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xA0404000 LD1W { <Zt1>.S-<Zt2>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000000100 | imm4 | 0 | 1 | 0 | PNg | Rn | Zt | 0
0xA040C000 LD1W { <Zt1>.S-<Zt4>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000000100 | imm4 | 1 | 1 | 0 | PNg | Rn | Zt | 0 | 0
0xA0004000 LD1W { <Zt1>.S-<Zt2>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2] A64 10100000000 | Rm | 0 | 1 | 0 | PNg | Rn | Zt | 0
0xA000C000 LD1W { <Zt1>.S-<Zt4>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2] A64 10100000000 | Rm | 1 | 1 | 0 | PNg | Rn | Zt | 0 | 0
0xA1404000 LD1W { <Zt1>.S, <Zt2>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000010100 | imm4 | 0 | 1 | 0 | PNg | Rn | T | 0 | Zt
0xA140C000 LD1W { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000010100 | imm4 | 1 | 1 | 0 | PNg | Rn | T | 0 | 0 | Zt
0xA1004000 LD1W { <Zt1>.S, <Zt2>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2] A64 10100001000 | Rm | 0 | 1 | 0 | PNg | Rn | T | 0 | Zt
0xA100C000 LD1W { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2] A64 10100001000 | Rm | 1 | 1 | 0 | PNg | Rn | T | 0 | 0 | Zt
0x8520C000 LD1W { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}] A64 1000010 | 1 | 0 | 01 | imm5 | 1 | 1 | 0 | Pg | Zn | Zt
0xC520C000 LD1W { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}] A64 1100010 | 1 | 0 | 01 | imm5 | 1 | 1 | 0 | Pg | Zn | Zt
0xA540A000 LD1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] A64 1010010 | 101 | 0 | 0 | imm4 | 101 | Pg | Rn | Zt
0xA560A000 LD1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] A64 1010010 | 101 | 1 | 0 | imm4 | 101 | Pg | Rn | Zt
0xA5102000 LD1W { <Zt>.Q }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] A64 1010010 | 1 | 0 | 001 | imm4 | 001 | Pg | Rn | Zt
0xA5404000 LD1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2] A64 1010010 | 101 | 0 | Rm | 010 | Pg | Rn | Zt

Description

Contiguous load of unsigned words to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.

Operation

if esize < 128 then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(64) base;
bits(PL) mask = P[g, PL];
bits(VL) result;
bits(msize) data;
constant integer mbytes = msize DIV 8;
boolean contiguous = TRUE;
boolean nontemporal = FALSE;
boolean tagchecked = n != 31;
AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, tagchecked);

if !AnyActiveElement(mask, esize) then
    if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then
        CheckSPAlignment();
else
    if n == 31 then CheckSPAlignment();
    base = if n == 31 then SP[] else X[n, 64];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        integer eoff = (offset * elements) + e;
        bits(64) addr = GenerateAddress(base, eoff * mbytes, accdesc);
        data = Mem[addr, mbytes, accdesc];
        Elem[result, e, esize] = Extend(data, esize, unsigned);
    else
        Elem[result, e, esize] = Zeros(esize);

Z[t, VL] = result;