fdiv

Floating-point Divide (Single)

FDIV <Sd>, <Sn>, <Sm>

Divides two single-precision floating-point registers.

Details

The Floating-point Divide instruction divides two single-precision floating-point registers.

Pseudocode Operation

Sd ← Sn / Sm
// Quotient truncated toward zero

Example

FDIV s0, s1, s2

Encoding

Binary Layout
00011110
001
Rm
000110
Rn
Rd
 
Format Float Data Proc
Opcode 0x1E201800
Extension F.P.

Operands

  • Sd
    Destination 32-bit floating-point register
  • Sn
    Dividend
  • Sm
    Divisor