fdiv

Floating-point Divide (Single)

FDIV <Sd>, <Sn>, <Sm>

Divides two single-precision floating-point registers.

Pseudocode Operation

Sd ← Sn ÷ Sm
N ← Sd[31]
Z ← (Sd == 0.0)
C ← (overflow or underflow)
V ← (invalid operation or overflow)

Example

FDIV s0, s1, s2

Encoding

Binary Layout
0
31
0
30
0
29
11110
28:24
00
23:22
1
21
Rm
20:16
0001
15:12
10
11:10
Rn
9:5
Rd
4:0
 
Format Float Data Proc
Opcode 0x1E201800
Extension F.P.

Operands

  • Sd
    Destination 32-bit floating-point register
  • Sn
    Dividend
  • Sm
    Divisor

Related

Other forms of fdiv

  • fdiv Floating-Point Divide (Scalar)
  • fdiv Vector Floating-Point Divide
  • fdiv SVE Floating-Point Divide
  • fdiv Floating-Point Divide (Half-Precision)
  • fdiv Floating-point Divide (Double)

More in F.P.

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2E403C00 FDIV <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 01110 | 0 | 10 | Rm | 00 | 111 | 1 | Rn | Rd
0x2E20FC00 FDIV <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 011100 | sz | 1 | Rm | 11111 | 1 | Rn | Rd
0x1EE01800 FDIV <Hd>, <Hn>, <Hm> A64 0 | 0 | 0 | 11110 | 11 | 1 | Rm | 0001 | 10 | Rn | Rd
0x1E201800 FDIV <Sd>, <Sn>, <Sm> A64 0 | 0 | 0 | 11110 | 00 | 1 | Rm | 0001 | 10 | Rn | Rd
0x1E601800 FDIV <Dd>, <Dn>, <Dm> A64 0 | 0 | 0 | 11110 | 01 | 1 | Rm | 0001 | 10 | Rn | Rd
0x650D8000 FDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 01100101 | size | 00 | 110 | 1 | 100 | Pg | Zm | Zdn

Description

Floating-point Divide (scalar). This instruction divides the floating-point value of the first source SIMD&FP register by the floating-point value of the second source SIMD&FP register, and writes the result to the destination SIMD&FP register. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();
bits(esize) operand1 = V[n, esize];
bits(esize) operand2 = V[m, esize];

boolean merge = IsMerging(FPCR);
bits(128) result = if merge then V[n, 128] else Zeros(128);

Elem[result, 0, esize] = FPDiv(operand1, operand2, FPCR);

V[d, 128] = result;